Graduate engineer at Arm in Budapest working on system IP microarchitecture specification and design, SystemVerilog RTL verification/debug, and formal bring-up of IP blocks, collaborating with design, validation and implementation teams. Core tech: SystemVerilog, AMBA bus protocols, Perl/Python scripting.
System IP microarchitecture specification and design
SystemVerilog RTL verification and debug
Formal bring-up of non-trivial IP blocks to achieve required quality levels
Collaboration with engineers across design, performance modelling, validation, and implementation to meet all functional requirements, performance, power and area goals
Bachelor or Masters degree in Electrical Engineering or Computer Engineering
Experience of block level RTL design and verification for non-trivial ASIC or FPGA developments
SystemVerilog knowledge
Familiarity with the Arm AMBA specifications or other bus protocols
Understanding of digital design including CPU, GPU and cache concepts, memory, I/O
Scripting skills with Perl or Python
Starting salary of HUF 10,950,000 per annum
Comprehensive rewards package
Clear opportunities to progress within the salary range at Arm
Mid-year and year-end reviews with two formal progression windows each year
Access to Grad-teach-Grads workshops, guest speaker series, and social events
Opportunity to join the Graduate Committee to develop planning, networking, and coordination skills
Invitation to the Global Graduate Conference
Relocation support for domestic and regional moves within Europe