"systemverilog" Jobs (359 open)

T

Senior FPGA Developer (SystemVerilog)

Terra Quantum · Germany - Hybrid

3 days ago

HybridSeniorautomationcloudethernetfpga

U

Senior ASIC Frontend Engineer - RTL & SystemVerilog

Upscale AI, Inc. · Kentucky, United States

1 month ago

Senioraiasicsystemverilog

C

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Cisco · Pune, India

4 months ago

aiasicciscoethernet

C

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)

Cisco · Pune, India

4 months ago

aiasicciscoethernet

C

ASIC Engineering Technical Leader | RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) | Exp - 12+ years

Cisco · Bangalore, India

5 months ago

aiasicautomationcisco

R

Sr Staff Engineer, Design Verification

Renesas Electronics · Bengaluru, KA, in

2 months ago

HybridStaffagileassemblybashperl

S

FPGA Engineer

Sapsol Technologies Inc · Melbourne, Florida, United States

2 months ago

asicfpgartlsystemverilog

O

(Sr./Staff) ASIC Design Engineer

OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. · Singapore

1 week ago

Staffautomationfirmwareobservabilityrtl

О

Инженер-программист ПЛИС / FPGA

ООО "СТЦ" · Город Санкт-Петербург

5 months ago

matlabpciesystemverilog

O

(Sr./Staff) ISP RTL Design Engineer

OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. · Singapore

1 week ago

Staffcmoscppsignal-processingsystemverilog

O

(Sr.) ISP RTL Design Manager

OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. · Singapore

1 week ago

Seniorcmoscpprtlsignal-processing

O

ISP RTL Design Engineer

OMNIVISION TECHNOLOGIES SINGAPORE PTE. LTD. · Singapore

1 week ago

cmoscppsignal-processingsystemverilog

A

Experienced Verification Engineer - System IP

ARM Hungary Kft. · Budapest

1 week ago

HybridHUF 21,250,000 – 28,750,000 / yearbashcppembedded-softwarefpga

A

Senior/ IC Design Engineer (Design Verification)

AUREXIS TECH PTE. LTD. · Singapore

2 weeks ago

Senioraiautomationgenerative-aimachine-learning

V

Senior Design Verification Engineer – Physical AI Compute

Velaura AI, Inc. · Santa Clara, CA

1 month ago

OnsiteSenioraiautomationcppfirmware

V

Design Verification Engineer – Physical AI Compute

Velaura AI, Inc. · Santa Clara, CA / Austin, Texas / Boston, MA

1 month ago

Onsiteaiautomationcppfirmware

O

(Sr.) ISP RTL Design Manager

ovt · Singapore

1 year ago

Seniorcmoscpprtlsignal-processing

O

(Sr./Staff) ISP RTL Design Engineer

ovt · Singapore

2 years ago

Staffcmoscppsignal-processingsystemverilog

S

Senior FPGA Engineer

Spyrosoft · Wrocław, Poland

1 week ago

SeniorContractaiautomationcppembedded-software

S

ASIC Digital Design, Sr Manager - 19159

Synopsys

Yesterday

Seniorautomationbashethernetpcie