Technical Staff - Design Engineering

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Job Description:

Microchip’s Communications Business Unit (CBU) develops high-performance networking, connectivity, and edge compute semiconductor solutions that power communications infrastructure, data centers, automotive systems, aerospace and defense platforms, and industrial applications. Our global team works across the full product lifecycle to deliver innovative products that enable the world’s most demanding connected systems.

The CBU Product Development team is engaged through the full device R&D cycle from concept, design and implementation stages. Once a prototype is available, we support embedded software development and system validation lab testing through to mass-market production release. We are an experienced chip team working with the latest semiconductor development tools and methodologies in advanced process technologies to develop state-of-the-art network devices.

We are seeking a Technical Staff Engineer in the CBU Product Development team who will be responsible for the architecture and technical leadership of communication semiconductor devices and subsystems. We are looking for an experienced hands-on technical leader who can directly contribute to the design at the block and top level of a device, solve challenging engineering problems with innovative solutions and mentor engineers. The individual will be a key member of the CBU’s Silicon Design Center in India with technical leadership and mentoring responsibilities.

Responsibilities may include:

• Architecture
  • Own or contribute to the architecture of leading-edge Communications Devices
  • Develop or enhance system-level understanding of Device Applications
  • Collaborate with Product Marketing, Applications Engineers, Vendors and Customers to identify, record and track Device Requirements
  • Design datapaths and partition functions; often employing complex, channelized techniques
  • Participate in concept and feasibility studies for Next-Generation Products and as well as ways to leverage our expertise into new Domains
• Technical Leadership
  • Deliver digital integrated circuits at the Device, Subsystem or Block level as an Architect, Designer or Team Leader
  • Supervise and mentor a small team of Design Engineers
  • Partner with a dedicated Verification Lead to deliver high-confidence designs
  • Design Digital Circuits based on Industry Standards and Market Requirements
  • Implement Designs in System Verilog RTL code utilizing low-power design principles
  • Interact with dedicated Synthesis and Physical Design/Layout teams and ensure quality of results
• Domain Expertise
  • Develop or enhance domains of Technical Expertise in Technologies, Flows or Standards
  • Contribute to Industry Standards, spanning different segments (data-centers, automotive, etc.), through submissions and participation in Study Groups
  • Provide subject-matter guidance to Development Teams within CBU
  • Enhance internal, proprietary Flows and Practices to improve efficiency and accuracy
• Cross Functional Responsibility
  • Collaborate with Software, Validation and Production Engineers to deliver production-worthy devices that integrate into a wider system
  • Communicate with the relevant parties regularly and effectively.

Requirements/Qualifications:

• Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering

• 12+ years related experience

• Excellent analytical and debugging skills and the ability to proactively solve issues

• Strong expertise in SystemVerilog RTL design and micro-architecture development.

• Deep hands-on experience with Lint, CDC, formal verification, logic synthesis, and static timing analysis.

• Strong understanding of physical design interactions, including timing, power, and congestion considerations.

• Solid experience with low-power design methodologies and flows.

• In-depth knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.

• Proficiency in scripting languages such as Tcl, Perl, and/or Awk.

• Experience with Synopsys or Cadence tool flows for synthesis, verification or STA (an asset)

• Experience with 28nm and smaller silicon process technologies (an asset)

Travel Time:

0% - 25%

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