Software Engineer, Control & Error Correction

About the role

We are hiring software engineers into Control & Error Correction, the team that builds the realtime engine inside the quantum computer: the software and digital logic that executes circuits, corrects errors and manages logical qubit operations, in NISQ mode today and fault-tolerant mode as the system scales. These components form the Realtime Quantum Control Plane, running across a mesh of FPGA cards wired to cryogenic hardware.

Time is the constraint. A correction has to come back inside about a microsecond. The scheduler allocates logical qubits across cards without adding latency of its own, and nothing on the hot path allocates, blocks or pauses. The limit is set by the physics, and no later optimisation recovers a missed budget.

The work spans the realtime scheduler, the NISQ pulse compiler in Rust and Python, logical measurement and Pauli frame tracking across chiplets, magic state distillation, and the decoder path from FPGA error monitoring through to the neural network decoders in the cluster. Compiler Services owns the executable contract, Automated Calibration Services keeps qubits in spec, and Platform & Infrastructure runs the cluster underneath.

Based at our Sydney facility, you will work with physicists and quantum information scientists on what a requirement means, and with the platform engineers who run the hardware underneath. This is a role for someone who reasons about worst case rather than average, and who wants to work where the latency budget is set by physics.

Role responsibilities

• Build and operate the realtime scheduler: logical qubit allocation across the FPGA mesh, the schedule and result pipeline, and the QIS controller
• Maintain and extend the NISQ pulse compiler that translates pulse-level operations into hardware instructions
• Implement logical measurement, Pauli frame tracking and inter-QPU operations across chiplets
• Work on the decoder path: error monitoring, offload and look-ahead, and the neural network decoder services in the cluster layer
• Build the orchestration around magic state distillation, so resource states are available when a logical gate needs them
• Design against hard deadlines: latency budgets, jitter, and hot paths with no allocation and no surprises
• Work across the boundaries between fabric, embedded processor, host and cluster, including memory-mapped interfaces, DMA and the card-to-card protocols
• Verify timing-dependent behaviour properly: simulation, reference models, and replay of recorded device data before anything touches a card
• Measure latency and jitter on the hardware rather than inferring them, and report the measured results
• Work with Compiler Services on what the control plane can execute, and with Automated Calibration Services on calibration duty cycles
• Bring up and operate the mesh alongside Platform & Infrastructure, including the CI/CD path onto real hardware
• Document the design, the interfaces and the measurements so the next engineer can extend what you built

Your experience

Essential

• 4+ years building systems software in production
• Rust or C++ at depth, plus Python for tooling, analysis and test
• Hard realtime experience, where a missed deadline is a failure rather than a slowdown: latency budgets, jitter, and allocation-free or lock-free hot paths
• Concurrency and synchronisation, and the discipline to keep the critical path simple
• Working close to hardware: memory-mapped IO, drivers, DMA, interrupts, and the contracts between software and logic
• Scheduling, allocation or queueing algorithms, and the ability to reason about worst case rather than average
• Strong computer science fundamentals, and comfort implementing an algorithm from a paper
• Testing systems whose behaviour depends on timing, including simulation and comparison against a reference implementation
• Measuring performance on the target hardware rather than by approximation
• Git workflow, code review and CI applied to hardware-facing code
• The ability to work with physicists and quantum information scientists on what a requirement means

Nice to have

• HDL design and verification in VHDL, Verilog or SystemVerilog, and the FPGA toolchain around it
• AMD Versal or Alveo cards, particularly the V80
• Quantum error correction, decoders, or matching and graph algorithms under a cycle budget
• Embedded and bare-metal work, including no_std Rust on ARM targets
• Kernel bypass, RDMA, DPDK, or other low-latency data paths
• DSP, pulse-level control, or closed-loop feedback in software
• Instrument control, scientific hardware, or precision timing and synchronisation
• Neural network inference under a latency budget, including quantisation
• Linux performance tooling: perf, tracing, and understanding where a microsecond went
• Quantum computing exposure of any kind (no physics degree required)
• Publications, open source contributions, or a realtime project you are willing to talk through