Job Details:

Job Description:

The Role and Impact Join our team as an SoC Logic Design Engineer where you will play a critical role in developing Intel's next-generation Client System-on-Chip (SoC) products. In this role, you will actively contribute to the RTL design and integration of high-performance IPs, ensuring exceptional functionality and quality for Intel's latest Client family of products. Your contributions will directly shape the technology that powers billions of devices worldwide. Business group This role is part of the Silicon and Platform Engineering Group (SPE), which drives innovation in semiconductor technology and system solutions. Our team is focused on developing cutting-edge Client SoCs, integrating advanced IPs, and delivering world-class silicon products. By joining SPE, you will contribute to Intel's mission of creating technology that enriches lives and powers the future of computing. Key Responsibilities - Develop and implement RTL design for internal IPs or integrate high-performance, bandwidth IPs into SoCs. - Collaborate closely with verification teams to support functional, feature, and integration validation. - Conduct front-end quality checks, including RTL static analysis, synthesizability assessments, timing/power convergence, netlist quality checks, and functional equivalence verification. - Work with design teams and architects to ensure functional integrity and overall chip quality. - Participate in cross-functional reviews and provide innovative solutions to optimize performance and design efficiency.

Qualifications:

Minimum Qualifications - Bachelor's degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science, or a related field with 0-1 years of hands-on experience in SoC RTL/Logic Design, demonstrated through internships, academic projects, coursework, or hands-on training. -OR- - Master's degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science, or a related field with no prior professional experience. - Proficiency in RTL design languages such as SystemVerilog and familiarity with verification methodologies like OVM/UVM. - Basic understanding of digital design concepts, including timing analysis, power optimization, and synthesis techniques. Preferred Qualifications - Experience with logic design, integration of high-performance IPs, or pre-silicon validation environments. - Familiarity with industry tools for RTL simulation, synthesis, and static timing analysis. - Strong problem-solving and communication skills to thrive in a collaborative team environment. We're looking for passionate individuals who aspire to shape the future of technology. If you're ready to take on exciting challenges and contribute to life-changing innovations, we encourage you to apply today.

Job Type:

College Grad

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Malaysia, Kulim

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.