BYTEDANCE PTE. LTD. · Singapore ·
The SoC Digital Design Engineer will design and implement hardware accelerators for video codecs and SoC subsystems using Verilog/SystemVerilog. The role involves architecture definition, RTL implementation, and cross-functional collaboration to optimize power, performance, and area for large-scale video platforms.
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About Us
Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create content.
Why Join ByteDance
Inspiring creativity is at the core of ByteDance's mission. Our innovative products are built to help people authentically express themselves, discover and connect – and our global, diverse teams make that possible. Together, we create value for our communities, inspire creativity and enrich life - a mission we work towards every day.
As ByteDancers, we strive to do great things with great people. We lead with curiosity, humility, and a desire to make impact in a rapidly growing tech company. By constantly iterating and fostering an "Always Day 1" mindset, we achieve meaningful breakthroughs for ourselves, our Company, and our users. When we create and grow together, the possibilities are limitless. Join us.
Diversity & Inclusion
ByteDance is committed to creating an inclusive space where employees are valued for their skills, experiences, and unique perspectives. Our platform connects people from across the globe and so does our workplace. At ByteDance, our mission is to inspire creativity and enrich life. To achieve that goal, we are committed to celebrating our diverse voices and to creating an environment that reflects the many communities we reach. We are passionate about this and hope you are too.
Job highlights
Positive team atmosphere, Career growth opportunity, Paid leave, 100+ mil users, Meals provided, Competitive compensation
Responsibilities
Team Introduction
Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Responsibilities
1. Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase.
2. RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation.
3. Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness.
4. Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization.
5. Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow.
Qualifications
Minimum Qualifications:
1. Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
2. 3+ years of experience in digital front-end design (open to highly promising candidates with less experience).
3. Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
4. Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
5. Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.
Preferred Qualifications:
1. Deep understanding of NPU architecture, HW/SW co-design and AI hardware acceleration.
2. Proven experience in SoC-level performance profiling and bottleneck analysis.
3. Hands-on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems).
4. Successful tape-out experience in advanced process nodes (7nm/5nm/3nm)
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