SoC Design Engineer

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Job Description:

As a SoC Design Engineer in the MPU group, you will work with our multi-sited global Silicon Development Team in design and development of complex SoCs. The work will include SoC design integration, microarchitecture, design verification, as well as supporting post silicon bring up.

Responsibilities

• Design and integration of complex IPs and subsystems into SoC
• Understanding SoC requirements and architecture specifications
• Understand IP specifications and work with IP/architecture/application teams to correctly integrate the IPs into SOCs, meeting the chip level requirements.
• Perform RTL coding
• Run RTL checks – Lint, CDC, RDC
• Develop verification plan for subsystems/SoC
• Collaborate with cross functional teams in architecture and IP evaluations, performance, power analysis, pre and post silicon validation
• Overcome design challenges, support achievement of verification goals, provide debug support
• Hold spec reviews, code reviews, coverage analysis, etc. to meet quality goals
• Support development of timing constraints and synthesis
• Power Estimation and Analysis

Requirements/Qualifications:

Qualifications/Requirements

• Good understanding of SoC architecture fundamentals and digital design
• Working experience in RTL coding using Verilog/SystemVerilog
• Understanding of ARM AMBA bus protocols
• Knowledge and exposure of complete SOC RTL to GDS to silicon release flow
• Proficiency in any one of commonly used scripting languages (Perl, Python, TCL)
• Knowledge of revision control tools such as SVN, GIT etc.
• Familiarity with AI-assisted development tools (e.g., Claude Code, Codex) for code generation/review, with understanding of responsible use (verification, IP/confidentiality, and compliance with company policies)
• Superior Written and Verbal Communication skills

Preferred Skills:

• Experience in ARM or RISC-V CPU based SoC development
• Hands on experience of C/System-C
• Experience/Understanding of verification using UVM

Required Education:

• BSEE minimum, MSEE preferred.

Travel Time:

0% - 25%

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