Silicon SoC Design Verification Engineer, HSIO
Google · Bengaluru, Karnataka, India ·
- Category
- Hardware
- Experience
- 8+ years
- Company size
- 1000+
Leads verification of high-speed I/O (HSIO) PHY interfaces for Google's custom silicon, owning sub-system and SoC-level testbench bring-up, running RTL/gate-level/timing regressions, and debugging complex waveforms through silicon bring-up. Core stack: SystemVerilog, C, OVM/UVM, and protocols like USB, PCIe, UFS, and MIPI.
As a High-Speed Input/Output (HSIO) Physical Layer (PHY) Verification Lead at Google, you will play a critical role in the development of our next-generation custom silicon. You will lead the verification strategy and execution for high-speed interfaces, ensuring seamless integration and flawless performance at both the sub-system and SoC levels. You will collaborate closely with global, cross-functional teams spanning design, architecture, and post-silicon validation to drive our custom hardware from concept to successful silicon bring-up.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Lead HSIO PHY integration verification at both the Sub-system and SoC levels.
- Drive SoC-level test case development and successfully port HSIO PHY IP-level test cases to the SoC environment.
- Execute and oversee regressions in RTL, Gate-Level Simulations (GLS), and Timing simulations and perform HSIO PHY virtual tester (VT) simulations across RTL, GLS, and Timing environments.
- Own testbench bring-up, including the integration of third-party Verification IP (VIP).Generate EVCD and bench collaterals for target test cases to support downstream validation.
- Perform deep waveform debugging and troubleshoot complex digital design and verification issues.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
- 8 years of experience in verification methodologies such as C, SystemVerilog and Open Verification Methodology/Universal Verification Methodology (OVM/UVM)-based constrained random verification.
- Experience of high-speed protocols including USB2/USB3, PCIe, UFS, MIPI, and in loopback test concepts.
- Experience with HSIO PHY Controllers and PHY+ controller test case porting.
Preferred qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- Strong understanding of SoC-level interfaces and the configurability of HSIO PHY registers.
- Experience leading verification modules or mentoring junior engineers in a complex SoC environment.
- Experience in scripting languages such as Python, Perl, SKILL, Tcl, or equivalent to build and automate verification flows.
- Track record of successfully taking complex mixed-signal/HSIO IP from the pre-silicon verification phase through to post-silicon validation.