Senior Staff Analog Mixed-Signal Design and Modelling Engineer

Location: This role is based at our Oxford, England (UK) office, with the option to work a few days a week remotely.
Travel: Up to 5%
Job ID: 1765

Role:

We are looking for a Staff Analog Mixed-Signal Design and Verification Engineer to join our Cryo-CMOS IC team at IonQ Oxford. In this role, you will design analog and mixed-signal blocks from specification through circuit design, simulation, layout, tape-out and silicon validation. You will also own top-level chip integration and modelling as a first-class part of our Cryo-CMOS development flow. In this you will build and maintain the model of the chip that the whole team simulates against, a mixed-abstraction model combining transistor-level circuits with Verilog-A/Verilog-AMS and SystemVerilog real-number behavioural blocks. You will decide which blocks are represented at which level of abstraction, keep the models faithful to the schematics and measured silicon. The full-chip model will then be used to verify the ASICs that control the quantum processor from room temperature down to a few kelvin.

You'll play an important part in shaping the design, modelling and verification methodology, standards and sign-off criteria that support our work in building the world's most advanced quantum systems.

Responsibilities:

In this position, you will build and maintain the model of the chip that the whole team simulates against, a mixed-abstraction model combining transistor-level circuits with Verilog-A/Verilog-AMS and SystemVerilog real-number behavioural blocks. These models will be derived form first-principles mathematics and correlated against schematic and measured silicon. You will decide which blocks are represented at which level of abstraction, keep the models faithful to the schematics and measured silicon. The full-chip model will then be used to verify the ASICs that control the quantum processor from room temperature down to a few kelvin.

You'll have the opportunity to set the design and modelling standards the programme signs off against, making trusted models to inform tape-out decisions, and raise the design and modelling capability of the engineers around you, contributing directly to the success of IonQ's quantum computing roadmap.

Key responsibilities include:

• Own the full-chip modelling strategy: model architecture, abstraction levels, accuracy targets and sign-off criteria used across the IC development flow
• Owning analog and mixed-signal blocks (references, DACs, switches, regulators, clock distribution) from specification through schematic design
• Own top-level integration: define block interfaces and specifications, assemble the top level, and run the full-chip mixed-signal simulations that verify the ASIC Develop Verilog-A and Verilog-AMS models of analog blocks and assemble them into a simulatable full chip
• Build real-number models so the full chip runs in digital verification and regression at practical speed
• Derive models from mathematics: turn a transfer function, a Z-parameter network description or a MATLAB analysis into robust Verilog-A with well-behaved tolerances
• Define and run model-versus-schematic correlation, keeping models in sync with design releases, and feed measured silicon behaviour, back into the models and the block designs
• Stand up mixed-signal co-simulation and regression (Cadence AMS Designer, Xcelium with Spectre) Lead block-level design reviews and mentor engineers on circuit design and modelling craft

Requirements:

To be successful, you will need deep analog and mixed-signal design and modelling experience, typically 10+ years. You will have designed blocks proven in silicon and models and used in production tape-out flows. You will bring expert transistor-level design of precision analog blocks (references, DACs, regulators, switches, clock distribution) taken through PVT and Monte Carlo, layout and silicon validation, together with expert Verilog-A and Verilog-AMS and strong real-number modelling.

You’d be a great fit with:

• Multiple tape-outs with responsibility for block design and top-level integration, including silicon bring-up and bench characterisation
• Strong mathematical foundations: linear systems, Laplace and z-domain analysis, network (Z-) parameters, noise and non-linearity
• Fluency in a production Cadence flow: Virtuoso, Spectre, Xcelium and AMS Designer or similar co-simulation environments, including parasitic extraction and post-layout sign-off
• SystemVerilog, plus MATLAB or Python/NumPy for analysis and model validation; scripting to automate model generation, checking and regression
• Cryogenic, space or other extreme-environment silicon experience will be highly beneficial, especially designing beyond foundry model validity using measured device data

We're looking for someone who can design a block to specification and model it at the right fidelity, derive a model from equations and implement it end to end. You should be able to judge what to model and at what abstraction, align designers, verification and systems engineers on what a model does and does not promise, and contribute effectively within a fast-moving, highly technical team.