Senior Design Verification Engineer

We are seeking a talented and driven Senior Design Verification Engineer with specialized knowledge and experience in emulation-based verification to join our engineering team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets are met prior to silicon tape-out. You will work closely with design, architecture, and validation teams to define verification plans, build robust testbench environments, and drive coverage to closure. A key focus of this position is leveraging emulation-based platforms to accelerate system-level verification, enabling early software bring-up and full-chip validation at scale. This is an excellent opportunity for a verification professional looking to deepen their expertise in cutting-edge verification methodologies and emulation technologies.

Responsibilities

• Develop and execute verification plans for IP-level and system-level designs.

• Build, maintain, and enhance UVM/SystemVerilog-based testbench environments including scoreboards, monitors, drivers, and coverage models.

• Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.

• Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) for system-level verification and performance validation.

• Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.

• Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.

• Develop and maintain assertion-based verification (SVA) to complement simulation and emulation efforts.

• Drive coverage closure and generate verification sign-off reports.

• Support software and firmware teams with early bring-up activities on emulation platforms.

• Continuously improve verification processes, flows, and infrastructure.

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Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.

• 5 – 8 years of professional experience in design verification of digital/mixed-signal designs.

• Strong proficiency in SystemVerilog and UVM methodology.

• Hands-on experience with emulation-based verification platforms (e.g., Cadence Palladium, Synopsys ZeBu, or Mentor Veloce).

• Solid understanding of digital design concepts including RTL design, synthesis constraints, and timing.

• Experience with constrained-random verification, functional coverage, and code coverage-driven methodologies.

• Proficiency in debugging complex hardware designs using simulation and emulation tools.

• Familiarity with scripting languages such as Python, Perl, or TCL for automation and flow development.

• Strong analytical and problem-solving skills with excellent attention to detail.

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Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.

• Experience with networking protocols such as Ethernet (10G/25G/100G/400G), TCP/IP, PCIe, or CXL.

• Knowledge of communication and interface protocols including AXI, AHB, APB, AMBA, I2C, SPI, or UART.

• Experience with formal verification tools and techniques (e.g., JasperGold, VC Formal).

• Familiarity with FPGA prototyping platforms and flows.

• Experience with power-aware verification (UPF/CPF).

• Prior exposure to SoC-level verification or full-chip integration verification.

• Knowledge of processor architectures (ARM, RISC-V, x86) and software-driven verification techniques.

• Experience with continuous integration (CI) and regression management frameworks.

• Familiarity with AI/ML application and architectures and experience, such as, creating Gen AI skills, marketplace, agentic applications, etc.

• Published work or patents in the area of design verification is a plus.