Senior Design Engineer : Custom Digital Hard Macros (Physical IP)

Role Overview

The Arm Solutions Engineering Physical IP group is building a team focused on the development of custom and semi-custom digital hard macros used across Arm CPU, GPU, NPU, and SoC products. These hard macros enable functionality that cannot be efficiently implemented using standard-cell methodologies alone, including power delivery, clocking structures, asynchronous interfaces, reliability mechanisms, and digital circuits interacting with analog and mixed-signal systems.

As a Design Engineer, you will contribute to the implementation and delivery of digital hard macros while developing a broad understanding of the complete macro development lifecycle. You will work across RTL, physical implementation, timing closure, simulation, characterization, and integration activities, gaining exposure to all aspects of Physical IP development.

The ideal candidate will possess strong implementation skills while also demonstrating curiosity and willingness to understand the underlying circuit, layout, simulation, and characterization aspects of macro development. Although not expected to be a specialist in analog design or characterization, the engineer should be capable of investigating issues across multiple abstraction levels and collaborating effectively with design, AMS, verification, and SoC integration teams.

Key Responsibilities

• Support design and implementation of custom and semi-custom digital hard macros.
• Develop and maintain RTL, timing constraints, implementation scripts, and automation flows.
• Execute synthesis, floorplanning, place-and-route, timing closure, physical verification, and signoff activities.
• Analyze and debug timing, power, congestion, DRC, LVS, and implementation issues.
• Review schematics and layout structures to understand macro operation and implementation tradeoffs.
• Support functional, gate-level, and mixed-signal simulation activities.
• Assist in characterization activities including timing, power, and functional model validation.
• Generate and validate macro deliverables including Liberty models, LEF abstracts, physical views, and integration collateral.
• Collaborate with AMS, DFT, verification, and SoC integration teams during development and product integration.
• Participate in silicon validation activities and support correlation of silicon behavior with pre-silicon expectations.
• Contribute to methodology improvements, scripting, and automation initiatives.

Required Skills & Experience

• 2-5 years of experience in digital design, physical implementation, Physical IP, or related semiconductor development.
• Good understanding of RTL design and digital design fundamentals.
• Hands-on experience with synthesis, floorplanning, place-and-route, static timing analysis, and physical verification.
• Familiarity with advanced implementation tools such as Cadence Innovus, Tempus, Genus, or equivalent.
• Understanding of timing constraints, SDC development, CDC concepts, and multi-clock designs.
• Working knowledge of transistor-level concepts, digital circuit operation, and custom layout fundamentals.
• Basic understanding of simulation methodologies including RTL, gate-level, and behavioral simulations.
• Familiarity with Liberty timing models and characterization concepts.
• Experience with Verilog/SystemVerilog and scripting languages such as Tcl or Python.
• Strong analytical, debugging, and problem-solving skills.
• Good communication and teamwork abilities.

Preferred Qualifications

• Exposure to hard-macro, memory, standard-cell, custom digital, or mixed-signal IP development.
• Experience at advanced process nodes.
• Exposure to low-power design methodologies and power-domain crossings.
• Understanding of metastability, asynchronous interfaces, and reliability concepts.
• Exposure to silicon validation or post-silicon debug activities

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