Senior CPU Design Verification Engineer

Senior CPU Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 7 years of experience with creating and using verification components and environments in standard verification methodology.
• Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, or a related field.
• Experience creating and using verification components and environments in standard verification methodology.
• Experience with verification techniques, and the full verification life cycle.
• Experience with performance verification of ASICs and ASIC components.
• Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
• Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, is highly beneficial for verifying processor cores or IP blocks.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.In this role, you will work as part of a Research and Development team.

• You will build verification components, constrained-random testing, and system testing, and drive verification closure.
• You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification.
• You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs.
• You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.

Responsibilities

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
• Identify and write all types of coverage measures for corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.Close coverage measures to identify verification holes and to show progress towards tape-out.