RTL Design Engineer, Sr Lead

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Key Responsibilities

· Develop detailed micro-architecture specifications from high-level architectural requirements.

• Design and implement synthesizable RTL using Verilog/SystemVerilog.
• Participate in design reviews and ensure design quality and compliance with coding guidelines.
• Perform RTL quality checks including:

o Lint analysis and cleanup

• • CDC/RDC analysis and closure
  • FSM and structural checks
• Develop and maintain design documentation including micro-architecture and interface specifications.
• Work closely with verification teams to define verification plans and resolve functional issues.
• Support synthesis, timing analysis, and timing closure activities.
• Develop and review SDC constraints for block-level and subsystem-level designs.
• Analyze and debug issues across simulation, synthesis, and implementation stages.
• Collaborate with DFT and physical design teams for successful integration and tapeout.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Required Qualifications

· Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.

• 5+ years of experience in ASIC/SoC front-end design.
• Strong knowledge of digital design fundamentals.
• Hands-on expertise in:

o RTL design using Verilog/SystemVerilog

• • Micro-architecture definition and documentation
  • Lint tools (SpyGlass, Questa Lint, or equivalent)
  • CDC/RDC tools (SpyGlass CDC, Questa CDC, or equivalent)
• Good understanding of clocking architectures, reset strategies, and low-power design concepts.
• Experience debugging RTL and simulation issues.

Preferred Qualifications

· Experience with synthesis flows using Design Compiler, Genus, or equivalent tools.

• Experience creating and reviewing timing constraints (SDC).
• Understanding of timing analysis concepts including setup/hold, clock domain crossings, and timing closure.
• Exposure to DFT methodologies and integration.
• Knowledge of low-power design techniques (UPF/CPF).
• Experience with complex SoC/IP development and integration.

Desired Skills

· Strong analytical and debugging skills.

• Excellent written and verbal communication.
• Ability to work independently and drive block ownership.
• Strong collaboration skills across architecture, verification, and physical design teams.

Nice to Have

· Experience working on high-performance CPU, DSP, AI/ML, networking, multimedia, or connectivity IPs.

• Scripting knowledge in Python, Perl, or TCL for automation and flow enhancement.

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