R&D Engineering, Architect - 18964

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade or more in the trenches of ASIC design, and you know that the best methodology is not the one that looks elegant in a slide deck but the one that actually ships silicon on schedule. You understand IP reuse at a level that goes beyond theory. You have debugged enough subsystem integration failures to know where the real friction points live, and you have built flows that eliminate them before they become someone else's three-week problem.

You are drawn to the intersection of AI and EDA not because it is trendy but because you see the practical leverage. You know which parts of front-end design are ripe for acceleration and which require human judgment, and you are comfortable working with agentic AI tools to prove the difference. You do not wait for perfect requirements. You prototype, you iterate, you show the value, and you bring people along.

Leadership for you is not about title. It is about being the person teams come to when a flow is broken, a methodology needs rethinking, or a new IP needs a reference design that actually works. You communicate complex tradeoffs clearly, whether you are talking to a verification engineer in Bangalore or a product manager in Mountain View. You have strong opinions loosely held, and you know when to push back and when to adapt.

What You'll Be Doing

• Apply agentic AI techniques to front-end design workflows, using internal and external AI tools to accelerate verification, synthesis, constraint generation, or test insertion
• Architect and deliver reference subsystem designs for Synopsys digital and mixed-signal IP portfolios that serve as templates for customer and internal use
• Troubleshoot, optimize, and debug design flows for IP teams and internal stakeholders, diagnosing issues across tools, scripts, and methodologies
• Build and document reusable design methodologies that scale across global teams and diverse project contexts
• Educate engineering teams on your work through technical presentations, design reviews, and hands-on mentorship
• Collaborate with EDA tool teams, IP developers, and customer-facing engineers to align methodology with real-world design challenges
• Drive adoption of best practices in front-end design, leveraging Synopsys tools like VCS, VC Spyglass, Fusion Compiler, and TestMAX in production flows

The Impact You Will Have

• Accelerate time-to-market for Synopsys IP customers by delivering proven subsystem designs and flows that reduce integration risk
• Shape how AI is applied to front-end design at Synopsys, establishing patterns that influence product roadmaps and customer engagements
• Elevate the technical capability of engineering teams through methodology you build, document, and teach
• Reduce design iteration cycles for internal IP teams by catching integration and flow issues early with robust reference implementations
• Influence the next generation of Synopsys EDA tools by providing real-world feedback from production design use cases
• Enable global teams to work more effectively by creating methodologies that are documented, repeatable, and adaptable across sites
• Strengthen Synopsys' competitive position in IP by ensuring our subsystems demonstrate best-in-class design quality and tool integration

What You'll Need

• 10 to 15 years of hands-on experience in IP or SoC design and verification, with a track record of delivering complex ASIC projects
• Deep expertise in at least one area of front-end design such as verification, constraints and synthesis, DFT and test insertion, or lint and CDC
• Strong working knowledge of agentic AI technologies and how they apply to design automation and EDA workflows
• Proficiency with Synopsys EDA tools including VCS, VC Spyglass, Design Compiler, Fusion Compiler, or TestMAX in production environments
• Solid programming and scripting skills in SystemVerilog, UVM, Tcl, Python, or similar languages used in design and verification flows
• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or equivalent practical experience. Advanced degrees are a plus.
• Demonstrated ability to document technical work clearly and communicate methodology across distributed, global engineering teams

Who You Are

• You can walk into a design review, spot the methodology gap that will cause pain three months from now, and propose a fix that the team actually adopts
• You are comfortable presenting technical work to senior engineers and directors without oversimplifying or losing the thread of what matters
• You treat debugging like detective work. You do not stop at symptoms, you trace root cause across tools, scripts, and design files until the issue is resolved
• You know how to balance perfection with pragmatism. You ship reference designs that are good enough to be useful and robust enough to be trusted
• You are a multiplier. When you solve a problem, you document it, automate it, and teach others so the problem stays solved
• You thrive in environments where priorities shift, requirements evolve, and the right answer is not always obvious from the start

The Team You'll Be Part Of

You will be a member of the Digital Methodology Interop Engineering team, a team of engineers dedicated to advancing IP and subsystem design excellence at Synopsys. The team collaborates across global sites, driving innovation in methodology, tool integration, and best practices. You will help shape the future of SoC design with Synopsys IP.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.