Principal/Staff Design Verification Engineer
Bitdeer · Singapore ·
- Seniority
- Principal
- Category
- Design
- Experience
- 10+ years
Leads verification strategy for complex IC designs, guiding teams to build test environments, debug RTL, and improve coverage using UVM, SystemVerilog, and RISC-V protocols.
You lead verification strategy and execution for complex IC designs. You guide verification engineers, develop test environments and sequences, run simulations and regressions, analyze coverage, debug RTL issues, create automation and reusable verification components, and collaborate with design, architecture, and physical implementation teams.
Responsibilities
- Lead verification strategy and execution for assigned DUT blocks
- Guide verification engineers in developing and maintaining verification test plans
- Develop verification environments, testbenches, and test sequences
- Create test patterns and stimulus scenarios for DUT functionality and corner cases
- Run simulations and analyze results
- Debug RTL issues with design engineers
- Manage regression testing across feature updates and bug fixes
- Track and improve functional and code coverage metrics
- Document test cases, results, coverage reports, and verification sign-off
- Develop automation scripts, reusable verification components, and VIP
- Collaborate with design, architecture, and physical implementation teams
- Mentor junior team members
Requirements
- At least 10 years of relevant experience in IC/SoC functional verification
- Strong debugging skills with RTL simulation and waveform analysis tools
- Proficiency in UVM, SystemVerilog, Verilog, and SVA
- Strong knowledge of AXI, NoC, and RISC-V protocols
- Ability to lead verification efforts and mentor engineers
- Bachelor’s degree or above in Microelectronics, Semiconductor Engineering, Electronic and Electrical Engineering, or a related field
Benefits
- Attractive welfare benefits
- Training and mentoring