Principal HS Digital Design Engineer (d/m/f)
ams OSRAM ·
- Seniority
- Principal
- Category
- Hardware
- Experience
- 10+ years
Principal high-speed digital design engineer at ams OSRAM in Pavia, Italy, working on digital IC design for communication and mixed-signal SoC products: RTL design in Verilog/SystemVerilog, synthesis, timing analysis, clock-domain crossing, and advanced CMOS nodes (FinFET/FD-SOI). Knowledge of UCIe/PCIe interfaces is an advantage.
Who we are looking for
- MSc or PhD in Electrical Engineering
- 10+ years digital IC design experience
- RTL design (Verilog/SystemVerilog)
- High-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantage
- Interface protocols and clock-domain crossing
- Synthesis and timing analysis
- Advanced CMOS node experience, including FinFET and/or FD-SOI, is required
Please contact Hana Krsul for further information via [email protected] or +43 664 9665611.