Principal Engineer, Design Verification - DDR Memory Subsystems
Altera Corporation · San Jose, California, United States ·
- Seniority
- Principal
- Category
- Design
- Experience
- 10+ years
Altera Corporation · San Jose, California, United States ·
At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, edge computing, and embedded systems.
About the Role
We are seeking an accomplished Principal Engineer, Design Verification to provide technical leadership for the verification of next-generation DDR memory subsystem IP integrated into Altera's industry-leading FPGA products. This individual will serve as the technical expert for memory subsystem verification, driving verification architecture, methodology, execution, and quality across multiple product generations.
This role is ideal for a recognized verification leader with extensive experience verifying complex DDR memory controllers, PHYs, and high-speed memory interfaces in advanced ASIC or FPGA designs.
Responsibilities
Serve as the technical lead for Design Verification of complex DDR memory subsystems across multiple FPGA product families.
Define and drive verification architecture, methodology, and strategy for DDR controllers, PHYs, training logic, calibration flows, and memory subsystem integration.
Architect scalable, reusable UVM/SystemVerilog verification environments capable of supporting multiple product generations.
Develop comprehensive verification plans utilizing constrained-random verification, assertions (SVA), functional coverage, scoreboarding, protocol checking, and regression automation.
Drive verification closure through rigorous coverage analysis, debug methodologies, and metric-based execution.
Partner closely with Architecture, RTL Design, Physical Design, Firmware, System Validation, and Silicon Engineering teams throughout the product lifecycle.
Lead root-cause analysis of complex subsystem integration, timing, protocol, and performance issues.
Influence memory subsystem architecture by providing verification-driven feedback during early design phases.
Mentor senior verification engineers while establishing organization-wide Design Verification best practices.
Drive continuous improvements in verification infrastructure, automation, CI/CD workflows, regression efficiency, and reusable IP verification methodologies.
Support post-silicon bring-up, characterization, and system validation activities to ensure successful product deployment.
At Altera, you'll help define the future of programmable computing by developing the memory subsystem technologies that power next-generation AI, cloud, networking, and edge applications. As a Principal Engineer, you'll have the opportunity to shape verification strategy across multiple product generations, influence architectural decisions, mentor world-class engineering teams, and solve some of the industry's most challenging memory subsystem verification problems.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - $299,200 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline.
15+ years of Design Verification experience developing complex ASIC, SoC, or FPGA products.
10+ years of experience verifying DDR memory subsystems, including memory controllers and PHY architectures.
Extensive expertise with SystemVerilog, UVM, SystemVerilog Assertions (SVA), constrained-random verification, functional coverage, and verification planning.
Deep understanding of modern memory technologies including:
DDR4
DDR5
LPDDR4
LPDDR5
HBM/HBM2/HBM3
Strong knowledge of:
DDR PHY architectures
Memory Controller design
Memory initialization and training sequences
Calibration algorithms
AXI and AMBA interconnect protocols
Cache coherency and memory subsystem integration
Proven experience verifying high-performance memory interfaces within large SoC or FPGA environments.
Demonstrated success leading verification efforts for highly complex subsystem or chip-level designs from specification through silicon validation.
Strong debugging experience using industry-standard simulators, waveform analysis tools, protocol analyzers, and regression infrastructure.
Excellent communication skills with the ability to influence technical direction across cross-functional engineering organizations.
Preferred Qualifications
Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
Experience verifying additional high-speed interfaces such as PCIe, Ethernet, CXL, UCIe, HBM, or SerDes.
Experience with formal verification methodologies and formal property checking.
Experience with emulation platforms, FPGA prototyping, and post-silicon validation.
Proficiency with scripting languages such as Python, Perl, Tcl, or Shell for automation and infrastructure development.
Experience implementing CI/CD pipelines and scalable regression frameworks.
Demonstrated leadership defining Design Verification methodologies across large engineering organizations.
Experience mentoring senior engineers and serving as the technical authority for complex verification programs.