Principal Design Engineer – High-Speed Interconnect

Responsibilities:

Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems, including PCIe, CXL, and UALink, across multiple silicon products. Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, register definitions, and synthesizable RTL, ensuring detailed execution and delivery.

Drive the development process from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery. Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality, bandwidth, latency, power, area, and timing targets, encouraging a culture of inclusion and teamwork.

Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs. Lead technical reviews, debug cross-functional issues, improve building methodologies, and mentor engineers, ensuring outstanding performance and reliability.

Required Skills and Experience:

• 8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.
• Deep hands-on expertise in SystemVerilog and the development of sophisticated, high-performance digital subsystems.
• Deep understanding of PCIe, CXL, and UALink, covering transaction flows, ordering, flow control, retries, error handling, host/device integration, memory expansion, and coherent connectivity.
• Experience with coherent or non-coherent interconnects, cache hierarchies, memory systems, and high-speed I/O subsystems.
• Strong understanding of AXI, CHI, ACE, APB, streaming interfaces, buffering, arbitration, scheduling, and backpressure.
• Experience with CDC, RDC, reset sequencing, low-power build, lint, X-propagation, formal verification, synthesis, timing analysis, and waveform debug.
• Ability to convert architectural requirements into clear microarchitecture documents and high-quality RTL.
• Proven technical leadership, communication, and delivery skills across multi-functional teams.
• Bachelor’s or Master’s degree, or equivalent experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

'Nice to Have' Skills and Experience:

• Experience with PCIe Gen6 or later, CXL 2.0 or later, UALink, chiplets, or die-to-die connectivity.
• Knowledge of RAS, IDE, TDISP, security, memory pooling, CXL.cache, CXL.mem, and accelerator connectivity.
• Experience integrating third-party IP, PHYs, firmware-visible capabilities, PCIe configuration space, BARs, interrupts, and error-management features.
• Validated experience in delivering sophisticated RTL or subsystem builds on schedule and meeting functional, performance, power, area, and quality targets.

In Return:

When joining our team, you are joining a collaborative environment where leadership is about empowering others. We embrace new and different ideas and perspectives, because we believe the best innovation only happens in a diverse and psychologically safe environment.

We support flexible working and ask our teammates to come into the office at least two days per week for planning, design discussions, and other team activities.

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Hybrid Working

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