Lead Software Engineer - Low-Power Verification in , United States
Energy Jobline ATTB · US ·
- Seniority
- Lead
- Category
- Software engineering
- Experience
- 1+ years
Energy Jobline ATTB · US ·
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Join our team and help build the next of low-power verification software for the Palladium and Protium emulation and prototyping platforms.As a Lead Software Engineer on the Palladium and Protium UPF R&D team you will be responsible for improving UPF compilation performance and correctness, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.What you will doContribute to the UPF compilation flow -- improve compilation performance, reduce instrumented capacity, and add self-checks across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.Rebuild UPF documentation around end-to-end compilation workflows, backed by valid SystemVerilog and UPF examples, and keep code and docs in sync through example-driven checks.Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).Help consolidate and unify UPF compilation across Palladium and Protium.What we are looking forBS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.Working knowledge of IEEE 1801 UPF and RTL (Verilog, SystemVerilog, VHDL).Ability to read, review, and reason about C++ code and object-oriented designs.Scripting experience in Perl, Tcl/Tk, and/or Python.Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.Strong technical writing skills — able to author user guides, specifications, and workflow-first documentation.