WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As an HSIO Technical Lead, you will provide deep technical expertise and leadership in the validation of high-speed I/O subsystems—including PCIe, xGMI, UAlink, IFoE, and UCIe—on AMD platforms. You will work cross-functionally with design, architecture, signal integrity, package/board, firmware/software, quality, and system/platform teams to develop comprehensive validation strategies, execute detailed test plans, debug electrical and protocol issues, and continuously improve validation coverage and methodology. Your responsibilities include margining and PHY analysis to characterize and optimize interface robustness, as well as enabling and qualifying advanced interface features.
THE PERSON:
This role is ideal for an engineer who enjoys deep technical debugging, lab-based validation, high-speed interfaces, and solving difficult cross-functional problems. The most successful candidates combine strong HSIO fundamentals, disciplined execution, and the ability to translate ambiguous failures into structured technical actions.
Key Responsibilities
- Develop and execute comprehensive functional validation plans for the xGMI, PCIe and UALink link controllers, ensuring that all protocol, feature and performance requirements are met prior to product release.
- Validate controller operation at the transaction and data link layers, including configuration and capability space, enumeration, packet generation and handling, ordering rules, flow control and credit management, replay and retry mechanisms, and completion handling.
- Validate link training and link state management, including link training state machine transitions, recovery and retrain paths, width and speed negotiation, hot-plug and surprise-removal handling, and degraded-mode operation.
- Validate link power management, including active state power management, device and package state transitions, clock request handling, and entry and exit latency under active traffic.
- Design and execute protocol-level error injection, and verify that error detection, logging, containment and recovery behave as architected — including error reporting registers, poison generation and propagation, and firmware-first and machine-check flows.
- Verify register and configuration space correctness, including reset default values, access attributes and sticky behavior across reset domains, through automated comparison against the register specification.
- Lead complex debug activities, applying protocol analyzers, exercisers, register-level tracing and on-die telemetry to determine root cause, and correctly partition issues among controller logic, firmware, physical layer and platform software.
- Develop and maintain validation automation, test content and reporting infrastructure in Python, enabling results to be trended across silicon revisions, firmware builds and system configurations.
- Collaborate with design, architecture and pre-silicon verification teams to align coverage, correlate silicon behavior against simulation and emulation results, and ensure silicon findings are reflected in pre-silicon coverage models.
- Participate in design reviews and provide input on register maps, error logging definitions and DFx features to ensure adequate observability and controllability for post-silicon validation.
- Establish entry and exit criteria for each validation phase and provide the functional readiness recommendation at program milestones, supported by documented evidence.
- Mentor and provide technical direction to validation engineers, and act as the technical escalation point for internal platform teams, ODM and OEM partners, and customers.
- Ensure thorough documentation of validation methodology and results, and communicate status, risks and issues to project stakeholders and management.
Key Qualifications
- Extensive experience in post-silicon functional validation: Senior level experience in validating high-speed interface controllers, with demonstrated technical ownership of an interface or subsystem through at least one silicon program from power-on to production release.
- Strong understanding of industry interconnect standards and protocols: Thorough working knowledge of PCIe (Gen4 / Gen5 / Gen6) and of coherent socket-to-socket or die-to-die interconnects such as AMD Infinity Fabric (xGMI), UALink or UCIe, at the transaction, data link and link training layers.
- Depth in link controller architecture and behavior: Configuration and capability space, packet formats and ordering rules, flow control and credit management, replay and retry, link training state machines, power state transitions, and error detection, logging and containment.
- Proficiency in laboratory debug tools and methodology: Hands-on experience with protocol analyzers, exercisers and error-injection equipment, register-level debug through firmware, driver or JTAG interfaces, and the ability to establish root cause from captured protocol traces.
- Proficiency in scripting and programming languages: Python for test content, instrument control, automation and data analysis, with version control and code review as standard practice. Familiarity with C or SystemVerilog is advantageous.
- Working knowledge of platform firmware and software: BIOS/UEFI enumeration and configuration, ACPI, and Linux driver and IOMMU behavior as they relate to link controller operation.
- Demonstrated technical leadership and communication: Proven ability to lead cross-functional debug spanning design, firmware, signal integrity and platform teams, and to communicate findings clearly to both engineering and program management audiences.
LOCATION:
Penang, Malaysia
#LI-SJ1
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.