Junior Logic Design Engineer

Altera Corporation · Haifa, Israel · 5 months ago

Seniority: Junior
Category: Engineering design
Experience: 0+ years

ai cloud fpga rtl signal-processing systemverilog verilog

Job Details:

Job Description:

Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We drive innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.

We are seeking a Junior Logic Design Engineer to join our team in Haifa and support the development and optimization of mixed-signal and high-speed IPs for integration into full-chip designs. This role is ideal for early-career engineers looking to grow their hands-on design skills while working alongside experienced engineers.

Responsibilities

Logic Design & RTL Development:
Assist in creating logic design, RTL code, and simulations for IP blocks, functional units, and subsystems.
Architecture Support:
Contribute to architectural and microarchitecture discussions and implementation under guidance from senior engineers.
Mixed-Signal Exposure:
Learn and apply mixed-signal design concepts, including basic analog behavior modeling and circuit simulation, to support RTL development and optimization.
Design Quality & Optimization:
Support efforts to meet power, performance, area, and timing requirements, ensuring designs are suitable for physical implementation.
Verification Collaboration:
Participate in RTL verification activities, review test results, and help debug and resolve failing tests.
Cross-Team Collaboration:
Work with internal teams and support SoC customers to ensure successful IP integration and high-quality design delivery.

Qualifications:

0–2 years of experience in logic design, digital design, or a related field (internships, co-ops, and academic projects count).
Good understanding of digital design fundamentals, RTL (Verilog/SystemVerilog), and simulation concepts.
Familiarity with communication interfaces or high-speed design concepts is an advantage but not required.
Exposure to mixed-signal concepts, SerDes, PHYs, or signal processing through coursework or projects is a plus.
Strong problem-solving skills and eagerness to learn in a fast-paced, collaborative environment.
B.Sc. (or upcoming graduate) in Electrical Engineering or a related field.

Application Requirement

Applicants must include their academic grades sheet (transcript) as part of the application

Job Type:

Regular

Shift:

Shift 1 (Israel)

Primary Location:

Haifa, Israel

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.