FPGA Design Engineer Senior

York is seeking a Senior FPGA Engineer to develop advanced FPGA solutions for York's Avionics and Payload Engineering team. You will collaborate across electrical, software, systems, and test engineering, drive architectural decisions, and contribute to mission-ready hardware.

Senior engineers at York influence system-level design strategy, elevate engineering processes, and mentor others while maintaining hands-on technical ownership.

This role will be fully on-site in our Greenwood Village, Colorado office.

Key Responsibilities

Lead the scoping, design, validation, and maintenance of complex FPGA designs.
Write RTL using SystemVerilog and/or VHDL.
Simulate and validate designs at module and integrated system levels.
Guide system-level integration efforts and collaborative troubleshooting.
Debug FPGA designs using simulation tools and lab equipment.
Maintain clear and complete technical documentation.
Support design reviews and improve FPGA development processes.
Perform additional mission-supporting duties as needed.

What Success Looks LikeWithin your first months, you will:

Lead FPGA development for mission-critical subsystems.
Partner with multidisciplinary teams to deliver flight-qualified designs.
Improve verification workflows or architectural decisions that enhance reliability.
Advance York’s avionics technology through hands-on design leadership.

You’ll Thrive Here If You

Enjoy solving challenging technical problems collaboratively.
Communicate engineering decisions clearly across disciplines.
Appreciate both leadership responsibilities and hands-on design work.
Want to see your work progress from concept to spacecraft integration.

This role will not have direct reports.

Required Qualifications

B.S. or M.S. in Electrical or Computer Engineering.
4+ years of experience in FPGA design.
Strong FPGA/RTL design and debugging experience.
Experience with full product life cycle development.
Experience with Git or equivalent version control systems.
Strong understanding of clocking, reset architecture, and high-speed interfaces.
Experience with tools like Vivado/ChipScope, Libero, or Quartus/SignalTap.
Experience with UVM, assertions, random verification.
Familiarity with AXI, APB, or other AMBA protocols.
Ability to validate FPGA designs using simulation tools and lab equipment.
Ability to work autonomously and collaboratively.
U.S. Citizenship.
Ability and willingness to obtain security clearance.
Willingness to work full-time in office in Greenwood Village, CO.

Preferred Qualifications

Experience with scripting (Python, TCL, Make, shell).
Radiation effects mitigation experience.
Experience designing timing constraints and automated test environments.
Experience developing signal processing algorithms.