Ethernet Design Verification Engineer

Ethernet Design Verification Engineer
Role Summary: We are looking for an Ethernet DV Engineer to verify high-speed Ethernet IP and subsystems, ensuring full protocol compliance and functional correctness prior to tapeout.
Responsibilities:
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Develop and maintain UVM-based verification environments/testbenches for Ethernet MAC/PHY IP
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Write test plans and directed/random test cases covering Ethernet protocol layers (PCS, PMA, MAC)
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Verify compliance with IEEE 802.3 Ethernet standards across relevant speed grades (1G/10G/25G/50G/100G/400G)
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Perform functional coverage analysis and drive coverage closure
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Debug simulation failures and collaborate with design teams to root-cause issues
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Develop and reuse verification IP (VIP) for Ethernet interfaces
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Participate in regression testing and continuous integration for verification sign-off
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Support post-silicon validation and correlate simulation results with lab findings
Required Skills: SystemVerilog, UVM, Ethernet protocol knowledge (IEEE 802.3), Verification IP development, Simulators (VCS/Questa/Xcelium), scripting (Python/Perl/Tcl)
Experience: 5–16 years in DV/verification roles, Ethernet protocol experience strongly preferred