Design Verification Engineer
Fortaegis · Amsterdam, Netherlands ·
- Work mode
- Onsite
- Category
- Design
- Experience
- 5+ years
Fortaegis is a fast-scaling, highly ambitious and cutting-edge semiconductor company. We are looking for a Design Verification Engineer responsible for verifying RTL designs for FPGA and ASIC-based products. The role focuses on ensuring that system-level and block-level requirements are correctly implemented in hardware designs and identifying functional issues early. We are looking for candidates with not only an exceptional skillset, but also an exceptional mindset, willing to go above and beyond to make our hardware engineering team even better.
Responsibilities
- Develop and execute verification strategies for intricate FPGA and ASIC RTL designs
- Design, implement, and maintain verification environments, including automated test suites and infrastructure, following industry-standard methodologies
- Identify, debug, and document design issues, collaborating closely with design engineers to validate functionality and performance
- Implement coverage-focused verification approaches to achieve thorough verification of all design features
- Coordinate with design, architecture, and software teams to ensure smooth integration and verification of designs
- Stay up-to-date with verification tools, methodologies, and best practices
Requirements
- 5+ years of experience in RTL functional verification for FPGA and/or ASIC designs
- Advanced knowledge of SystemVerilog and UVM
- Hands-on experience with verification EDA tools (e.g., Siemens, Cadence, Synopsys)
- Strong analytical and problem-solving abilities with keen attention to detail
- Experience with formal verification techniques is a plus
- High-speed networking (Ethernet, PCIe) or cryptographic IP experience is advantageous
- Effective communication, teamwork skills and ability to collaborate across functions
- Ability to take ownership and solve problems beyond the scope of the job description, with a flexible, solution-oriented mindset