Design Team Manager, Servers, Google Cloud

As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.

In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
• Lead design activities at IP’s, subsystems, and System-on-Chips (SoCs).
• Plan, execute, track progress, assure quality, and report status of the assigned activity.
• Work closely with internal customers and support multiple activities and deliverables.
• Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in RTL design cycle from IP to SoC, from specification to production.
• 8 years of experience in execution teams management.
• Experience in the following areas: RTL design, design quality checks, physical design aspects of RTL coding, and power.

Preferred qualifications:

• Experience with synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
• Experience with a scripting language like Python or Perl.
• Experience with design for test and its impact on design and physical design.
• Knowledge of one of the following areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, ARM processors family.
• Knowledge of SoC architecture and assertion-based formal verification.
• Knowledge of high performance and low power design techniques.