ASIC Digital Design, Principal Engineer - 18708

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You understand that verification is not about writing tests, it is about building an environment where the right bugs cannot hide, and you have the scars from finding those bugs at 2am to prove it.

Leading a team does not mean delegating tasks, it means knowing when to step in, when to let someone struggle productively, and when to rewrite the testbench architecture because the current one will not scale. You have worked with RTL designers who swear their code is clean and architects who change the spec on Thursday, and you have learned to build verification strategies that survive both.

Memory protocols like DDR or LPDDR do not intimidate you. Serial interfaces, complex checkers, SystemVerilog assertions that actually mean something, these are tools you reach for without thinking. You care about functional coverage because it tells you what you have not tested yet, not because it is a metric someone asked for. At Synopsys, you will work on DesignWare IP that powers real products, with a team that takes verification as seriously as you do.

What You'll Be Doing

• Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff
• Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations
• Define test plans that cover corner cases, protocol compliance, and system-level interactions, then review and guide implementation across the team
• Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
• Extract, analyze, and drive functional coverage and code coverage metrics to closure, identifying gaps and adjusting strategy in real time
• Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and catch issues early
• Manage regression infrastructure and work with the infra team to keep verification cycles efficient and reliable

The Impact You Will Have

• Deliver verification signoff on IP cores that ship in millions of devices, ensuring they work correctly the first time in silicon
• Raise the bar for verification quality across the DesignWare team by mentoring engineers and evolving testbench architecture and methodology
• Catch critical bugs before tapeout that would otherwise cost months of schedule and customer trust
• Influence IP architecture decisions by surfacing verification insights early, when design changes are still cheap
• Help shape how the team adopts AI-assisted verification flows, improving efficiency without sacrificing rigor
• Contribute to Synopsys' leadership in IP by ensuring that what we deliver is not just feature-complete but robustly verified
• Build verification environments and strategies that other teams will reuse and learn from, multiplying your impact across the organization

What You'll Need

• Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 8+ years of hands-on verification experience
• Proven track record leading verification teams through IP project delivery, including planning, execution, and signoff
• Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow
• Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs
• Proficiency extracting and interpreting functional coverage and code coverage, and using those metrics to drive verification closure
• Experience verifying serial interface protocols and working through IP design and verification processes, knowledge of DDR or LPDDR protocols is a strong plus
• Demonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff, experience with AI-assisted verification tools is a plus

Who You Are

• You can explain a coverage hole to an architect in two sentences and walk out with a plan to close it
• You debug by hypothesis, not by adding print statements until something makes sense
• When a testbench is too slow or too brittle, you refactor it instead of working around it
• You give feedback that makes engineers better, not just feedback that makes the code pass
• You work across time zones and teams without losing context or creating confusion downstream
• You know when to push back on a design decision and when to adjust the verification plan to match reality

The Team You'll Be Part Of

You will join Synopsys' DesignWare IP Verification R&D team in Bangalore, working with a global group of experienced verification engineers who are responsible for ensuring the quality and reliability of IP cores that power semiconductors across the industry. This team collaborates closely with RTL designers, architects, and infrastructure engineers to deliver robust, production-ready IP.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.