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"uvm" Jobs

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"uvm" Jobs – Page 17 (344 open) | Jobyssey

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Q

FPGA Design & Verification Engineer

Quantbox Research · Bengaluru, Karnataka, India

4 months ago

Full timeethernetfpgapciertl

A

Senior ASIC Verification Engineer

AFRY · Malmö, Skåne County, se

5 months ago

Seniorasiclinuxnetworkingsystemverilog

M

Design Verification Engineer

Micron Technology · Hyderabad - Phoenix Aquila, India

6 months ago

airisk-assessmentsystemveriloguvm

S

Design Verification Engineer

SambaNova Systems · San Jose, California, United States

Yesterday

Full timeUSD 120,000 – 200,000 / yearagentic-aiaibashfirmware

A

Design Verification Engineer

Apple · San Diego

1 week ago

USD 142,300 – 214,300 / yearasicbashfirmwareperl

M

Principal Silicon Design Verification Engineer

Microsoft · United States, California, Santa Clara

2 weeks ago

OnsitePrincipalUSD 142,800 – 274,800 / yearazurecloudonedrivepcie

Q

SoC Design Verification Engineer (Up to Principal Level)

Qualcomm · Ho Chi Minh, Hồ Chí Minh, Vietnam

3 weeks ago

OnsitePrincipalautomationbashfirmwarefpga

R

Design Verification Engineer（SoC機能検証エンジニア）(1)

Renesas Electronics · Kodaira, jp

1 month ago

agileaisystemverilog

M

Design Verification Intern, MS - Summer 2027

Marvell · Santa Clara, CA

1 month ago

InternInternshipaiasicchatgptcloud

M

Design Verification Intern, BS - Summer 2027

Marvell · Santa Clara, CA

1 month ago

InternInternshipaiasicchatgptcloud

C

Senior Specialist, Electrical Engineering, FPGA Engineer (FOS) , Cincinnati, Ohio, US, Full Time/Per, (MK)

Central Business Solutions, Inc · Cincinnati, Ohio

1 month ago

SeniorFull timecsharpembedded-systemsfirmwarefpga

A

Staff Design Verification Engineer – SoC and eFPGA

Analog Devices · US, CA, San Jose, Rio Robles

2 months ago

StaffFull timeUSD 150,978 – 218,624 / yearaiautomationci-cdcpp

G

Chief FPGA Architect (PL) - Global Opportunity

Grupo Oesía · Rivas-Vaciamadrid, ES

3 months ago

C levelfpgaiso-9001rtlsystemverilog

株

1216_SoC Hardware / Group Leader

株式会社ティアフォー · （雇入れ直後 / Initial Assignment）東京都品川区北品川一丁目12-10 ジャコムビル、東京都品川区北品川一丁目19-4 泉北品川ビル及び労働者の自宅 Jakom Building, 1-12-10 Kitashinagawa, Shinagawa-ku, Tokyo, Izumi Kitashinagawa Building, 1-19-4 Kitashinagawa, Shinagawa-ku, Tokyo, and Employee’s home （変更の範囲 / Potential Changes）会社の定める場所（テレワークを行う場所を含む）/Any location designated by the company (including remote work locations) 就業の場所における受動喫煙を防止するための措置に関する事項：就業場所全面禁煙 Smoking is prohibited at all work locations (completely smoke-free environment).

3 months ago

RemoteContractaiclaude-codecppethernet

R

HPC SoC RTL Verification Engineer/Leader

Renesas Electronics · Kodaira, jp

3 months ago

E

DV - Staff (+) Verification Engineer -  AMS modeling

eliyan · Bay Area, Vancouver or Toronto

4 months ago

OnsiteStaffperlpythonsystemverilogtcl

U

CHEF INSTRUCTOR

Universidad del Valle de México · Puebla, UVM, MX

2 months ago

uvm

S

Service Engineer or Technician (m/f/d) for spectroscopy products (UV–Vis-NIR, FTIR, RF, Raman) in full time (37,5 hours/week) to join our European Headquarters in Duisburg.

Shimadzu Europa GmbH · Duisburg, Nordrhein-Westfalen, Deutschland

3 days ago

HybridFull time

X

Application Engineer, Sales Support (m/w/d), UV-Desinfektion – Wasser & Abwasser

Xylem · Herford

1 month ago

S

Content Creator (m/w/d) (Content Creator)

SK UV Gele GmbH · Mönchengladbach, Germany

3 weeks ago

Full timephotoshoppremiere-pro

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