Vývojári a analytici softvéru a aplikácií inde neuvedení
Tachyum s.r.o. · Bratislava-Staré Mesto, Slovakia ·
- Employment
- Part time
- Experience
- 6+ years
Our team is looking for Design Verification engineers with hands-on experience in multiple projects with verification using UVM based methodology. Candidates must be able to work and integrate third party verification IP and be able to work with protocols like PCIe, Ethernet, DDR4 etc.
Basic Qualifications
Bachelors or Masters in Electrical or Computer Science
6-8 years of relevant verification experience in UVM
Ability to adapt to a start-up fast paced dynamic environment
Required Experience
Hands on experience with System Verilog constraints writing, structures and classes.
Hands on experience of executing multiple projects using UVM based SOC verification. Ability to create or enhance existing UVM sequences and tests. Knowledge of UVM constructs: uvm_sequence, uvm_phases, uvm_callback.
Ability to build or help in building user constraints based random verification infra-structure using UVM for block level and/or Chip level verification.
Strong understanding of waveform debugging, RTL simulation.
Ability to integrate third party Bus Functional Model, integrate it in the existing environment and build verification infra-structure on top of that.
Ability to write assertions, cover properties, cover points.
Ability to generate functional coverage, code coverage data and going through it with designers, driving the effort of closing the coverage holes and/or resolving them to closure with designers.
Experience with running Gate Level simulation.
Help in test plan development for block and Chip level and driving it to closure by capturing test plan items in tests.
Preferred Experience
Familiarity with basic synthesizable RTL designs (flops, fifos Clock domain crossing) is a plus.
Strong familiarity with any of these protocols: PCie, Ethernet (100G and above), DDR4.
Ability to create regression scripts to run individual and batch jobs on grid.
Basic Qualifications
Bachelors or Masters in Electrical or Computer Science
6-8 years of relevant verification experience in UVM
Ability to adapt to a start-up fast paced dynamic environment
Required Experience
Hands on experience with System Verilog constraints writing, structures and classes.
Hands on experience of executing multiple projects using UVM based SOC verification. Ability to create or enhance existing UVM sequences and tests. Knowledge of UVM constructs: uvm_sequence, uvm_phases, uvm_callback.
Ability to build or help in building user constraints based random verification infra-structure using UVM for block level and/or Chip level verification.
Strong understanding of waveform debugging, RTL simulation.
Ability to integrate third party Bus Functional Model, integrate it in the existing environment and build verification infra-structure on top of that.
Ability to write assertions, cover properties, cover points.
Ability to generate functional coverage, code coverage data and going through it with designers, driving the effort of closing the coverage holes and/or resolving them to closure with designers.
Experience with running Gate Level simulation.
Help in test plan development for block and Chip level and driving it to closure by capturing test plan items in tests.
Preferred Experience
Familiarity with basic synthesizable RTL designs (flops, fifos Clock domain crossing) is a plus.
Strong familiarity with any of these protocols: PCie, Ethernet (100G and above), DDR4.
Ability to create regression scripts to run individual and batch jobs on grid.