System Performance Modeling Engineer/Architect

Build full-chip performance models that predict chip performance before RTL exists and as the design evolves. Model tile arrays, NoC, and memory systems; analyze workloads and bottlenecks; evaluate architectural trade-offs; correlate predictions with implementation results; and provide performance references for architecture and verification teams.

Responsibilities

• Build and maintain cycle-approximate and analytical models in C++, SystemC, and Python
• Produce roofline and bottleneck analyses
• Model NoC contention, memory bandwidth, and QoS under realistic traffic
• Generate and parameterize traffic scenarios for architecture studies
• Run architectural sweeps across tile count, local-memory size, NoC topology, bandwidth, memory channels, and QoS
• Turn modeling results into architecture recommendations
• Correlate model predictions against RTL, emulation, FPGA, and silicon
• Quantify and close the modeling-to-reality gap
• Provide performance references and golden-model hooks for performance and verification teams
• Maintain dashboards and trade-off presentations

Requirements

• 5+ years in performance modeling or architecture for SoCs and accelerators
• Strong C++ and Python skills
• Experience with SystemC or a comparable cycle-approximate modeling framework
• Understanding of memory hierarchy, bandwidth and latency trade-offs, interconnect and NoC behavior, and roofline reasoning
• Ability to model subsystems and turn results into architecture decisions
• Ability to work from incomplete specifications and collaborate across architecture, design, and software teams
• Familiarity with NoC or interconnect modeling, memory-controller behavior, or 3D-DRAM/HBM bandwidth analysis
• Exposure to compiler/dataflow co-design for accelerators
• Experience correlating models against RTL, emulation, or silicon
• Background with tile-based or dataflow architectures

Benefits

• Attractive welfare benefits
• Training and mentoring