Staff Engineer, Physical Design

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities will include, but are not limited to:

• Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits
• Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions
• Leading all aspects of and managing the layout process including floor-planning, placement, and routing
• Performing verification processes with modeling and simulation using industry standard simulators
• Contributing to cross group communication to work towards standardization and group success
• Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product
• Proactively solicit mentorship from Standards, CAD, modeling, and verification groups to improve the design quality
• Driving innovation into the future Memory generations within a dynamic work environment

Design Planning & Top-Level Integration

• Perform top-level virtual flat placement to explore partitioning options and validate hierarchy quality before commit.

• Implement top-level global routing to derive congestion, timing, and pin-feasibility signals that drive planning decisions.
• Own partition creation: block shaping, abutment, channel/keep-out definition, and power-domain planning.
• Drive pin optimization / pin cutting — pin placement, alignment, and count reduction guided by top-level routing.
• Plan and implement repeater / feedthrough insertion: budget top-level nets, place repeaters, and manage crossings across partition boundaries.
• Generate block-level constraints (timing budgets, boundary SDC, ILM/ETM models, physical constraints) directly from the design planning tool and hand them off to block owners.
• Perform top-level assembly: integrate block-related work (LEF/DEF/GDS/ETM/ILM), close top-level timing, DRC, LVS, and EM/IR, and iterate ECOs to convergence.

Block-Level APR

• Implement full APR flow (init → floorplan → place → CTS → route → ECO → sign-off) on digital blocks; own block-level STA sign-off across corners alongside DRC, LVS, EM/IR, and antenna closure.
• Set up new project and revision environments — collateral (SDC, netlist, LEF, QTM), stdlib migrations, and constraint authoring.
• Debug and correlate synthesis vs. APR vs. STA (PPA regressions, DRV, size_only/don't_touch strategy, scan chain stitching).

Methodology & Automation/AI

• Automate flows in Tcl / SKILL / Python; extend internal make-based flow and contribute to shared analysis tooling and dashboards.
• Improve the processes efficiency and quality leveraging AI flows
• Partner with STA, DFT, CAD, and custom-layout teams; document methodology and provide mentorship to engineers gaining experience.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [email protected]

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