Staff Embedded Firmware Engineer — Platform Controller (Zephyr RTOS)

Role Overview

We are building the firmware that runs on our platform management controller: a Zephyr-based system responsible for power sequencing, rail telemetry, board health, and secure boot on next-generation silicon. This Staff Embedded Firmware Engineer — Platform Controller (Zephyr RTOS) owns firmware from pre-silicon bring-up through production release, working shoulder-to-shoulder with design, DV, and systems teams.

What you’ll do

• Design, implement, and maintain Zephyr RTOS firmware for platform management controller, including device drivers, subsystem integration, and application-level services.
• Write and upstream-quality-review drivers against Zephyr's driver model — devicetree bindings, Kconfig, init levels and priorities, struct device APIs.
• Deploy and maintain lightweight ML inference on target for anomaly detection and predictive fault analysis; own the path from trained model to running firmware.
• Perform post-silicon bring-up: first-boot debug, clock and reset validation, bus enumeration, triage of RTL-versus-firmware ambiguity with design teams.
• Debug hard problems using JTAG/SWD, ETM/ITM trace, protocol analyzers, and logic analyzers — including intermittent, timing-dependent, and multi-master bus failures.
• Build and extend CI: unit tests, Twister test suites, hardware-in-the-loop regression, static analysis gates.
• Write the documentation your teammates and customers will actually rely on — design docs, bring-up guides, register-level notes, release notes.

Required qualifications

• 8–10 years of professional embedded firmware development in C, with meaningful exposure to modern C++ or Rust.
• Deep, hands-on RTOS experience on 32-bit microcontrollers (Arm Cortex-M or RISCV) — scheduling, priority assignment, ISR design, synchronization primitives, and the failure modes each one produces.
• Strong grasp of serial protocols at the wire level: I2C, SPI, UART — arbitration, clock stretching, timing parameters, and how they break.
• Practical debugging skill with JTAG/SWD debuggers, oscilloscopes, logic analyzers, and protocol decoders.
• Comfort with the toolchain: Git, GCC/Clang, CMake, Python scripting, and CI systems.
• Applied AI/ML knowledge — at minimum, a working understanding of model training and deployment workflows, quantization and its accuracy cost, inference latency and memory budgeting on constrained targets, and honest judgment about when ML is and is not the right tool for a control problem.
• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

Preferred qualifications

Strong candidates will have direct experience with several of the following. We do not expect all of them.

RTOS and platform

• Zephyr RTOS in production: devicetree, Kconfig, west workspaces, SYS_INIT and device init ordering, Twister, upstream contribution history.
• Bare-metal and boot-path firmware, including boot ROM code, secure boot chains, and ROM-to-application handoff.
• On-chip bus fabric familiarity — AMBA APB / AHB — and what a fabric-level stall or misconfigured bridge looks like from the firmware side.

Peripherals and subsystems

• PMBus and SMBus — command sets, PEC, ALERT handling, multi-master and bus-recovery behavior.
• QSPI flash: XIP, DMA-driven transfers, dual/quad modes, flash programming and update paths.
• GPIO expanders and pin multiplexing; PWM and PIT/timer peripherals for control loops and precise sequencing.
• Watchdog design — windowed watchdogs, task-level petting strategies, and failure-mode analysis.
• Interrupt controller configuration nested and prioritized interrupts, latency measurement and reduction.
• Telemetry subsystem design: ADC sampling strategy, calibration, scaling, and out-of-band reporting.
• Debug and trace infrastructure — ETM/ITM, SWO, coresight, trace-based performance and timing analysis.
• AI based coding experience is must