Sr. RFIC Design Engineer, Amazon Leo
Amazon · San Diego, California, USA ·
- Seniority
- Senior
- Employment
- Full time
- Category
- Hardware
Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Come work at Amazon!
The Role:
As a Sr. RFIC Design Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment.
As a member of the RFIC team, you will be responsible for the architectural definition, design, simulation, layout, and extracted simulation for transmit and receive front-ends from data converters to LNAs and PAs. Strong focus will be on creating power and cost optimized solutions for a given system performance.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
• Collaborate with communications systems, digital design, and chip implementation teams to specify and implement transceivers and RFIC front-end models which will delight future Kuiper customers.
• Lead implementation of area/power-efficient RFIC chips with multiple transceiver chains with integrated PLLs from concept to production.
• Work closely with packaging/HW/EE/FW teams to ensure seamless system integration providing best value for Kuiper customers.
• Collaborate with the digital design team to define analog/digital boundary requirements for circuit calibration, clock generation, and timing.
• Explore architectures for mm-wave and RF circuits like VCOs, mixers, phase shifters, LNAs, PAs, LO distribution, frequency multipliers and dividers, and envelope/power detectors, and make detailed presentations on power/area/performance trade-offs.
• Design and simulate on-chip inductors, baluns, and power combiners in tools such as EMX or HFSS.
• Perform circuit layout, RLC extraction, and run extracted simulation across various corners to make sure designs are robust and can be taken to volume production.
• Specify bench and production test plans for your designs.
The Role:
As a Sr. RFIC Design Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment.
As a member of the RFIC team, you will be responsible for the architectural definition, design, simulation, layout, and extracted simulation for transmit and receive front-ends from data converters to LNAs and PAs. Strong focus will be on creating power and cost optimized solutions for a given system performance.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
• Collaborate with communications systems, digital design, and chip implementation teams to specify and implement transceivers and RFIC front-end models which will delight future Kuiper customers.
• Lead implementation of area/power-efficient RFIC chips with multiple transceiver chains with integrated PLLs from concept to production.
• Work closely with packaging/HW/EE/FW teams to ensure seamless system integration providing best value for Kuiper customers.
• Collaborate with the digital design team to define analog/digital boundary requirements for circuit calibration, clock generation, and timing.
• Explore architectures for mm-wave and RF circuits like VCOs, mixers, phase shifters, LNAs, PAs, LO distribution, frequency multipliers and dividers, and envelope/power detectors, and make detailed presentations on power/area/performance trade-offs.
• Design and simulate on-chip inductors, baluns, and power combiners in tools such as EMX or HFSS.
• Perform circuit layout, RLC extraction, and run extracted simulation across various corners to make sure designs are robust and can be taken to volume production.
• Specify bench and production test plans for your designs.