Sr. Memory Validation Engineer
Ambarella · US Headquarters ·
- Seniority
- Senior
- Employment
- Full time
- Category
- Industrial engineering
- Experience
- 4+ years
Ambarella · US Headquarters ·
Job Description
About the role
Memory is where a lot of system-level problems come to die. Marginal timing, a corner-case power state transition, a customer platform that fails one boot in ten thousand — these issues are expensive to reproduce, slow to root-cause, and they tend to come back.
We're hiring an engineer onto our ASIC design team to change that. You'll own the data and automation layer for our memory subsystem: building the test infrastructure that catches instability early, turning lab and field data into insight, and feeding what you learn back into the design of our next-generation memory controllers.
This is a role for someone who likes both the oscilloscope and the dataframe. You'll spend time in the lab on silicon bring-up and just as much time writing the automation that means nobody has to do that debug by hand next time.
What you'll do
What you'll build
What we're looking for-
Required
Nice to have
1. Silicon bring-up or post-silicon validation experience on a production program
2. Signal integrity fundamentals: eye diagrams, jitter, and timing margin analysis on high-speed interfaces
3. Experience with low-power state validation (self-refresh, power-down, DVFS-style transitions)
4. Statistical analysis, ML, or dashboarding experience applied to hardware validation data
5. Firmware or driver-level exposure to the memory stack
Why this role
Running memory at state-of-the-art speeds is genuinely hard, and it gets harder every generation. The margins shrink while the variables multiply: load, power, temperature, process spread. Silicon doesn't behave the way the simulations said it would, so the work becomes finding calibration and training approaches that hold up on real parts, in real systems, across the full operating envelope.
Then there's the second problem, which is doing all of that fast. A characterization flow that works in the lab is not a production flow. Getting from one to the other, reliably and on schedule, is its own engineering challenge.
And then there's DVFS, which is a beast in its own right. Validating frequency and voltage transitions without giving up stability or power targets means chasing failures that only appear at specific transition boundaries under specific conditions.
If that sounds like the kind of problem you want to spend your time on, this role has a steady supply of them. It also comes with real visibility: the data you produce goes to the architects planning the next generation, the field teams supporting customers today, and the validation teams qualifying silicon tomorrow. The decisions you influence show up in shipping products.
The base salary range is $152,000 - $179,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.