Software Engineer, Compiler (Middle-end)
FuriosaAI · Seoul, South Korea ·
- Seniority
- Middle
- Category
- Software engineering
FuriosaAI is seeking a Software Engineer to develop middle-end compiler optimizations for their AI inference hardware. The role involves designing IR abstractions, scheduling algorithms, and performance models to improve the efficiency of deep learning workloads on specialized compute platforms.
About FuriosaAI
FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&D lab in Lisbon.
Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence for every enterprise.
About the Role
The compiler plays a central role in FuriosaAI’s mission to build high-performance, energy-efficient AI systems. As modern deep learning models continue to evolve in structure and execution behavior, the compiler’s abstractions and optimization strategies must advance in parallel. Our goal is to build a production compiler that delivers high performance across a broad range of workloads.
The middle-end tackles key optimization problems that determine how tensor programs execute on FuriosaAI hardware. These involve a large, tightly coupled space of decisions, including tiling, fusion, data layout, hardware mapping, and scheduling. We formulate these problems at the right level of abstraction for the TCP architecture and optimize them jointly.
In this role, you will identify and take ownership of compiler problems in real models and production workloads. You will turn those insights into general compiler solutions. You will design IR abstractions, optimization passes, program analyses, or planning algorithms, then integrate and validate them in the compiler.
Key Responsibilities
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IR, Semantics, and Lowering. Design and evolve intermediate representations, semantics, and lowering transformations that connect tensor programs to efficient hardware execution.
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Global Optimization and Execution Planning. Develop performance models, search and solver techniques, and optimization algorithms that produce efficient execution plans across the program.
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Scheduling and Resource Management. Optimize execution schedules and hardware resource allocation.
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Program Analysis and Verification. Build dependence and alias analyses, race detectors, and compiler checks that validate transformations and catch correctness issues early.
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Hardware/Software Co-design. Contribute compiler and workload insights to future hardware generations, and evaluate proposed architectures before implementation in silicon.
Minimum Qualifications
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Bachelor's degree in Computer Science, Mathematics, or a related technical field.
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Foundational knowledge of compiler design and optimization passes.
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Ability to abstract complex hardware/software constraints into logical algorithms and solve problems through rigorous reasoning.
Preferred Qualifications
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Master's or PhD in Programming Languages, Compilers, Program Analysis, or related fields.
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Research or industry experience with compiler infrastructures like LLVM or MLIR.
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Experience developing code generators, instruction schedulers, or high-performance kernels for specialized accelerators (NPU, GPU, etc).
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Experience applying search, constraint solving, or mathematical optimization (ILP, SMT, dynamic programming, heuristic search) to compilation, scheduling, or resource allocation problems.
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Experience building analytical or learned performance models for hardware.
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Experience applying program analysis techniques to optimize performance or ensure program correctness.
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Experience with functional programming languages, particularly in the design of large-scale software systems.
Why Join FuriosaAI
The defining bottleneck of the AI era is building the right hardware and software stack to run it at global scale. Furiosa is solving this challenge holistically from the ground up.
With our flagship chip, RNGD, in mass production today and our next-generation platform in development with Broadcom, we are proving that full-stack, tensor-native compute is the future of AI infrastructure. This is a pivotal moment to join our team, right as we accelerate our global expansion.
At Furiosa, you will:
Solve AI’s Most Urgent Challenge. Help build the high-performance, energy-efficient inference hardware and software required to fulfill the promise of advanced AI.
Pioneer Full-Stack Co-Design. Work with teams that are architecting solutions from silicon up through the compiler (featuring innovations like Tensor Contraction Language and Virtual ISA) and serving frameworks.
Ship Real-World Silicon, Software, and Solutions. Turn breakthrough technology into commercial deployment. RNGD is in mass production with TSMC and running live enterprise workloads for global leaders like LG AI Research and Samsung SDS.
Partner With the Industry's Best. Collaborate across an elite global ecosystem that includes TSMC, Broadcom, SK Hynix, and GUC.
Do Your Life’s Best Work. Join a brilliant, low-ego, mission-driven team in a high-trust environment that values autonomy, intellectual curiosity, and shared ambition.
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