SoC Power Architect, Google Cloud, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Power Architect, you will not just design chips; you will define the energy efficiency of the infrastructure that powers Google services worldwide.

In this role, you will be at the intersection of architecture, logic design, physical implementation, and system software. You will own the power architecture for next-generation custom SoCs (System on Chips), making critical trade-offs between performance, thermal constraints, and power delivery to build the most efficient computing platforms on the planet.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Define and own the SoC power architecture, including complex power domains, clocking structures, and power delivery network (PDN) solutions to achieve optimal performance-per-watt.
• Architect sophisticated power management policies, including dynamic voltage and frequency scaling (DVFS), power gating, and state strategies. Define the hardware/software interface for the Power management unit (PMU) and provide power management specifications.
• Lead collaboration across architecture, RTL, physical design, packaging and validation teams to establish power budgets and specifications. Ensure power requirements are met from concept to tape-out.
• Develop high-fidelity power and performance models to evaluate architectural features early in the design cycle. Drive pre-silicon power estimation and analysis to guide design decisions.
• Lead post-silicon power analysis, correlating lab measurements with pre-silicon models to close the loop and improve future methodologies.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 10 years of experience in ASIC/SoC architecture or design with a focus on power optimizations.
• Experience developing or using power and performance modeling tools to drive architectural trade-offs.
• Experience in low-power design techniques (e.g., UPF/CPF, multi-voltage islands, power gating, clock gating, etc.) and on-chip power management IP.

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience in the design and analysis of full-chip power integrity, including interactions between clocking, reset, and power sequencing.
• Experience with post-silicon bring-up, power calibration, thermal management, and debugging in a lab environment.
• Experience with data center or server SoC power architecture and management requirements.
• Experience with industry-standard EDA power tools (e.g., Conformal LP, Power-Artist, PrimeTime-PX, Joules) and simulation environments.
• Familiarity with modern workload analysis (AI/ML, transcoding, networking) and their impact on SoC power profiles.