SoC Physical Design Engineer (Senior/Lead)
Qualcomm · Bangalore, India ·
- Work mode
- Onsite
- Seniority
- Lead
- Category
- Hardware
- Experience
- 3+ years
Company:
Qualcomm India Private LimitedJob Area:
Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Experience: 3-6 Years
Location: Bangalore
Job Responsibilities
Own end-to-end physical design implementation from Netlist to GDSII for complex SoC/IP blocks.
Drive Floorplanning, Power Planning (PDN), Placement, CTS, Routing, STA, and Timing Closure.
Perform physical verification including DRC, LVS, and signoff checks.
Collaborate with RTL, STA, DFT, Verification, and CAD teams to achieve design and tapeout goals.
Debug and resolve timing, congestion, IR drop, and physical design challenges.
Support successful chip tapeouts on advanced technology nodes.
Required Skills
3-6 years of hands-on experience in SoC/ASIC Physical Design.
Strong expertise in Floorplanning, PDN, Placement, CTS, Routing, and Timing Closure.
Experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, and Calibre.
Good understanding of physical verification, power integrity, and signoff methodologies.
Experience working on advanced nodes (16nm and below preferred).
Strong debugging, problem-solving, and communication skills.
Preferred
Experience in high-performance CPU, GPU, AI, Mobile, Networking, or Multimedia SoCs.
Candidates from leading semiconductor product companies are strongly preferred.
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