SOC Hardware Engineer, Quality and Reliability, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an SOC Hardware Quality and Reliability Engineer, you will ensure the long-term reliability and robustness of our semiconductor products by owning the physical qualification hardware enablement space. Your core duties will focus on driving IC-level qualification hardware enablement, establishing robust component-level stress testing methodologies, and governing qualification hardware quality to guarantee our semiconductor platforms meet the highest industry bars. You will partner across cross-functional organizations and global engineering sites to define physical stress requirements, evaluate IC hardware testing limits during early design stages, and oversee qualification hardware integrity from NPI through high-volume production. Your stamp on quality, reliability, and performance has the potential to shape the technology that goes into our cutting-edge data centers, affecting millions of Google users worldwide.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Own technical specifications, architectural definitions, and physical power-on of custom qualification vehicles (HTOL load boards, ESD fixtures, Latch-Up rigs); drive external layout vendors to achieve seamless electrical correlation with ATE environments.
• Govern execution quality of applied stresses; define electrical, thermal, and telemetry parameters on test vehicles to ensure uniform, valid stress profiles without unintended overstress or setup artifacts.
• Lead the end-to-end engineering delivery life-cycle for qualification hardware; map and drive critical cross-functional dependencies across internal validation and product engineering teams to ensure on-time readiness.
• Serve as primary technical interface for external PCB layout houses, fabrication shops, and component suppliers; manage design reviews, track lead times, and enforce delivery schedules.
• Lead laboratory troubleshooting for qualification hardware anomalies; isolate setup/socket faults from true silicon failures and drive supplier corrective actions (CAPA) when board excursions occur.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related field, or equivalent practical experience.
• 4 years of experience in hardware engineering, with a focus on authoring technical specifications, reviewing electrical layouts, and driving verification of semiconductor test or validation platforms.
• Experience working within specialized semiconductor reliability or test laboratories, including configuring component Burn-In ovens, high-power stress load boards, ESD simulators, and Latch-Up (LU) test setups.

Preferred qualifications:

• Proven experience managing the design execution cycle of complex multi-layer test vehicles through third-party design houses or layout vendors from concept sign-off to laboratory delivery.
• Proven experience defining and verifying electrical correlation baselines between environmental stress setups and High-Volume Manufacturing (HVM) ATE environments.
• Demonstrated experience driving deliverables and managing quality standards with external layout vendors, board design houses, or hardware component suppliers across multiple global geographies.
• Strong background analyzing the "quality of stress" factors, including power distribution networks (PDN), signal integrity degradation across extended thermal loops, and transient load behavior during reliability cycles.