SoC Design and Verification

• At least 7 years of experience in RTL Design verification of SoCs (VHDL, Verilog, System Verilog).
• At least 2 years of experience in PCIe Logical Phy and PIPE interface pre-silicon verification.
• Creating System Verilog / OVM test benches at the IP & SOC level and validating.
• At least 1-year experience in any of the Scripting: Perl, Tcl, python.
• Experience with low power design.
• Must have Tool expertise in any: DC, NCSim, Verdi, Spyglass-DFT, LP, TXV, CDC (preferred DC, NC-Sim, and Spyglass).
• Experience in clock gating, synthesis, CDC, and ECO process is a PLUS.
• Protocol: PCIe (mandatory), Ethernet, Bridges.
• Knowledge of ASIC design methodologies and flows.
• Ability to Manage and conduct training for the team.
• Worked with companies and seen at least a couple of tape-outs
• Project management capabilities.
• Ability to work with teams spread across geography with excellent communication skills.

• Bachelor’s degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education.
• At least 11 years of experience with Information Technology.

** U.S. Citizens and those who are authorized to work independently in the United States are encouraged to apply. We are unable to sponsor at this time.

Note:-

1. This is a Full-Time & Permanent job opportunity for you.
2. Only US Citizen, Green Card Holder, GC-EAD, H4-EAD & L2-EAD can apply.
3. No OPT-EAD, H1B & TN candidates, please.
4. Please mention your Visa Status in your email or resume.

** All your information will be kept confidential according to EEO guidelines.