Snr ASIC Design Engineer at Qblox – Delft | Jobyssey

ASIC Design Engineer

Join us at Qblox as we revolutionize the landscape of quantum computing! Our technology is used around the globe by world-class research teams to build a cutting-edge control stack for industrial-scale quantum computers.

Our distributed architecture allows parallel qubit readout, control, and intercommunication, ultimately interacting with physical qubits using high-frequency analog signals. Imagine what it takes to talk to 10,000 qubits with

nanosecond-level synchronization and all-to-all connectivity, and you will understand the massive microarchitectural, design, and verification challenges we face as we transition our logic to dedicated silicon.

We foster a highly collaborative culture. You will take ownership of your projects, influence technical decisions, and work alongside analog/mixed-signal engineers, digital verification specialists, embedded software developers, and physicists.

Your Role:

 Deconstruct Requirements & Design: Evaluate system requirements to

architect and implement robust, high-performance digital logic and IP

blocks.

 Front-End Flow Ownership: Drive designs through the front-end ASIC

flow, including RTL coding, linting, clock domain crossing (CDC)

analysis, and initial synthesis.

 Verification Collaboration: Write block-level self-checking testbenches

and collaborate with the verification team to expand top-level UVM

environments.

 Architectural Influence: Propose innovative changes to chip

architecture, power-saving strategies, and team methodologies.

 Cross-Functional Sparring: Act as a core technical sparring partner to a

diverse engineering team, continuously pushing for better ways of doing

things.

Enough about us, what about you?

To thrive in this role, you should bring:

 Experience: 8+ years as a digital design engineer within an R&D or fabless ASIC environment, with a proven track record of successful silicon tape-outs/deliveries.

 RTL & Architecture: Deep fundamental knowledge of digital design, IP development, and RTL coding using VHDL and/or Verilog.

 EDA Tools & Flow: Strong experience with standard ASIC front-end EDA tools, processor/bus-system architectures (e.g., AMBA AXI/AHB protocols), and synthesis.

 Timing & Constraints: Solid understanding of static timing analysis (STA) constraints and timing closure methodologies.

 Mixed-Signal Familiarity: Understanding of analog/mixed-signal chips or IP (e.g., ADC/DAC interfaces, PLLs).

 Automation & Tools: Proficiency in scripting to automate design workflows (Python, Tcl, Shell) and version control (Git).

 Communication: Strong communication and collaboration skills.

Optional Nice-to-Haves:

 Active experience with advanced verification frameworks (UVM).

 Prior experience with DFT (Design for Test) insertion, scan chains, and BIST.

 Experience with modelling and simulation in MATLAB / Simulink.

 Strong background in DSP and signal-processing filters.

 Familiarity with AI agentic workflows and automation within the design flow.

 Experience or a strong interest in the Quantum Computing field.

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