Senior VLSI Design Engineer (IO Design, DDR) with 5 to 7 years of experience

Actively contribute to provide High Speed DDR IO solutions for next generation Memory in advanced CMOS technology nodes.

Designing high Speed IO Blocks, Powerbus analysis, Jitter / High speed timing closure

Work closely within the team, cross functional teams like Layout, verification, actively participate in technical discussions and reviews.

Contribute to or propose innovative design solutions and design methodologies for future generation

• Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design)
• Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment.
• 4+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable.
• NAND Flash Design knowledge is plus
• Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit design including DLL, Rx, Tx and clocking circuits
• Knowledge of High Speed layout guidelines, analog layout techniques, including floor-planning, matching, shielding and parasitic optimization
• Familiarity with package/board/Power integrity /signal integrity constraints is a plus.
• Strong communication skills & circuit design knowledge is preferred.
• Tool knowledge: spice tools: finesim, hspice & other flows
• Good automation & scripting knowledge is plus.

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