Senior Staff Front-End Engineer IP Integration

The role develops and integrates PCIe-related IP blocks, evaluates performance, supports verification closure and functional coverage, debugs pre-silicon and post-silicon issues, and contributes to software development through scripting automation.

Responsibilities

• Implement Verilog RTL for PCIe IP sections
• Integrate and configure PCIe IP
• Evaluate PCIe IP performance
• Support verification closure and functional coverage
• Contribute to design verification and debug pre-silicon and post-silicon issues
• Support software development

Requirements

• Master’s or Bachelor’s degree in Electrical Engineering or Computer Engineering
• Five or more years of semiconductor or high-technology research and development experience
• Verilog RTL development experience with industry-standard tools in an SoC or IP environment
• PCIe IP integration experience
• Strong understanding of PCIe architecture and logic design
• Strong problem-solving and debugging skills
• Ability to use Perl, Shell, or TCL scripting languages

Benefits

• A culture that values authenticity and diversity of thoughts and backgrounds
• An inclusive and respectful environment with open workspaces and start-up spirit
• Opportunity to network with industry pioneers and enthusiasts
• Ability to contribute directly to the future of the digital asset industry
• Involvement in new projects and process or system development
• Personal accountability, autonomy, fast growth, and learning opportunities
• Attractive welfare benefits
• Training and mentoring opportunities