Senior Staff Engineer Analog Mixed-Signal Design (f/m/div)

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Join the thinkers, builders, and problem solvers behind tomorrow’s technology. As a Senior Engineer Analog Mixed-Signal Design on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

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Your role
Key responsibilities in your new role

• Lead end-to-end ADC design – architecture definition, circuit implementation, and silicon bring-up of high-performance converters (SAR, Pipeline, Sigma-Delta, Flash, or hybrid topologies)

• Design critical analog/mixed-signal building blocks including OTAs, comparators, DACs, sample-and-hold circuits, references, and clocking/bias circuits with clear ownership of performance, power, area, and cost trade-offs

• Drive comprehensive pre-silicon verification – transistor-level to chip-level simulations, Monte Carlo, corner, and worst-case analyses – through to post-silicon lab characterization and debug

• Develop behavioral and architectural models of ADC and mixed-signal blocks using Python and/or MATLAB for system-level simulation and early design exploration

• Collaborate cross-functionally with digital design, physical design, and CAD teams to ensure successful tape-out, and interface with customers and product teams to align technical solutions with requirements

• Mentor junior and mid-level engineers, lead design reviews, and actively contribute innovative ideas based on state-of-the-art trends in mixed-signal and ADC design

  
  

Your profile
Qualifications and skills to help you succeed

• An M.Sc. or Ph.D. in Electrical Engineering, Microelectronics, or a related field

• 5+ years of hands-on industry experience in analog and mixed-signal IC design, with a proven track record of successful silicon tape-outs and product bring-up

• Deep expertise in one or more ADC architectures (SAR, Pipeline, Sigma-Delta, Flash, or hybrid topologies) and analog building blocks such as OTAs, comparators, references, LDOs, and switched-capacitor circuits

• Solid understanding of mixed-signal design including clock distribution, digital calibration, timing closure, and asynchronous logic

• Proficiency with EDA tools (Cadence Virtuoso/Spectre, ADE XL, HSPICE, or equivalent), the full custom IC design flow, and experience with advanced CMOS process nodes (e.g., 130nm–12nm)

• Skills in Python and/or MATLAB/Simulink for automation, scripting, and system-level modeling, as well as knowledge of digital calibration techniques

Salary pay information:

Austria

We offer competitive salaries and additional benefits based on your performance, experience, and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.

Padova

Location

Indicative salary range

Padova, Italy*

€ 43.440 – € 59.730

*The stated salary comprises annual base pay and target variable compensation. The starting salary is determined using objective, gender neutral criteria, including relevant experience, qualifications, and role scope; prior compensation is not requested or considered. Employees also benefit from a comprehensive total rewards package, which may include further compensation and benefit elements depending on local regulations and company policies.

#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
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Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.

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Maria Pollai-Schlintl