Senior SoC/RTL Design Engineer

This individual independently plans, performs the moderately-defined responsibility for the digital architecture, design, Verilog RTL coding, implementation, and verification of next generation wireless and wired ASIC’s for the delivery of cutting edge hardware and software products across established wireless standard/protocol in the mobile, networking, computing and consumer electronics markets. Designs, verifies and delivers complex ASICs from functional specification to the final product. Investigate solutions for concept designs and evaluate architecture proposals. Also responsible for high speed digital and mixed signal board design; including requirements gathering, schematic capture, component placement, layout review, production, verification and trouble-shooting. Perform component evaluation, circuit optimization, and unit level testing of mobile phone and other wireless designs in an engineering environment. Test and debug of test platform hardware and digital circuit component level and RF debugging. Responsibilities will include supporting design engineers with the set-up and execution of complex tests and component evaluation related to base band designs. Perform circuit level debug, and provide feedback and assistance to design engineers by compiling test data into reports and presentations. Works closely and interacts with cross-functional teams to plan and execute verification and validation subsystems for integration into SoC’s (System on Chip) for mobile applications. Design hardware that meets the performance and power goals and adheres to the interface requirements while maintaining a scalable, reusable design that can be easily verified. Acts as a strong contributor at design reviews and project meetings.