Senior Digital Implementation Engineer
Xinyx Semiconductor Design Services Inc · Filinvest, Alabang, Metro Manila ·
- Seniority
- Senior
- Category
- Customer success
- Experience
- 5+ years
Experienced Physical Design or Digital Back - end engineer, capable of driving and leading and/or developing needed RTL to GDSII flow. Responsible for developing internal methodologies to achieve reductions in development cycle time and performance improvements. Assist the Supervisor/Manager in resource planning and management for the successful service delivery to clients including team development. Lead project teams and may include unit.
Key Responsibilities:
● Full RTL to GDSII (Synthesis and Place and Route) implementation including timing closure
● Floorplanning and IP Macro placement planning
● Power planning, implementation and optimization
● Perform Clock Tree Synthesis (CTS), Placement, Routing and Static Timing Analysis (STA)
● Perform Physical Verification (DRC, ERC, LVS, ANTENNA checks)
● Reliability checks like EM violations check and Signal Integrity issues like crosstalk
● Generation of GDSII, SPEF, SDF and other model files
● Lead quality assurance checks to ensure that quality standards are met
● Client, tasks and project management
● Drives and leads process improvement and develop innovative solutions in Physical Design flow
● Drives strategic planning, preparing and completing action plans within the team.
● Resolve problems, determining system improvements and implementing change. Collaborate
with cross-functional teams (LE, CHAR, DA, others) to drive issues and resolutions.
● Develop training material and conduct training/coaching for Physical Design Engineers
Educational Background/Qualifications:
● BS/MS in Electrical Engineering, Electronics Engineering, Computer Engineering and/or
Engineering in a related field.
● With at least 5 years of experience on Back - end Design flow specifically with Physical Design
flow.
Meta Competencies:
● Excellent communication and presentation skills, both written and spoken English
● Aggressive in learning, strong problem solving, decision-making and troubleshooting skills
● Ability to work in a team operating across multiple sites
● Ability to plan and organize project activities
● Ability to lead Physical Design teams and may include units.
Key Responsibilities:
● Full RTL to GDSII (Synthesis and Place and Route) implementation including timing closure
● Floorplanning and IP Macro placement planning
● Power planning, implementation and optimization
● Perform Clock Tree Synthesis (CTS), Placement, Routing and Static Timing Analysis (STA)
● Perform Physical Verification (DRC, ERC, LVS, ANTENNA checks)
● Reliability checks like EM violations check and Signal Integrity issues like crosstalk
● Generation of GDSII, SPEF, SDF and other model files
● Lead quality assurance checks to ensure that quality standards are met
● Client, tasks and project management
● Drives and leads process improvement and develop innovative solutions in Physical Design flow
● Drives strategic planning, preparing and completing action plans within the team.
● Resolve problems, determining system improvements and implementing change. Collaborate
with cross-functional teams (LE, CHAR, DA, others) to drive issues and resolutions.
● Develop training material and conduct training/coaching for Physical Design Engineers
Educational Background/Qualifications:
● BS/MS in Electrical Engineering, Electronics Engineering, Computer Engineering and/or
Engineering in a related field.
● With at least 5 years of experience on Back - end Design flow specifically with Physical Design
flow.
Meta Competencies:
● Excellent communication and presentation skills, both written and spoken English
● Aggressive in learning, strong problem solving, decision-making and troubleshooting skills
● Ability to work in a team operating across multiple sites
● Ability to plan and organize project activities
● Ability to lead Physical Design teams and may include units.