Senior Backend Design Automation Engineer — New Process Node Enablement
Altera Corporation · San Jose, California, United States ·
- Seniority
- Senior
- Category
- Backend
- Experience
- 8+ years
- Company size
- 1000+
- Salary
- USD 149,100 – 215,925 / year
Altera Corporation · San Jose, California, United States ·
The Senior Backend Design Automation Engineer will develop and maintain backend design flows for new semiconductor process nodes, integrating PDKs and EDA tools to support FPGA design teams. The role involves modernizing design infrastructure and applying automation and AI/ML techniques to optimize flow development and regression testing.
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
You will be working in the Design Automation group as a senior owner of Backend design automation flows, responsible for bringing up the design environment for new process nodes, carrying it through to production use, and providing ongoing project support. Our design teams are our users: you will work directly with design team leads, domain representatives, and technology enablement partners to understand what a new node demands of the Back-End flows, then define, build, deploy, and support the methodology that gets designers to sign-off.
New node bring-up and project support are the core of the job, not a side project. Every new process node arrives as a PDK, a standard-cell library, and a set of technology collateral that nothing in our flow stack has seen before. You will be one of the engineers who turns that raw delivery into a working design environment—intercepting PDK and Foundation IP from the foundry, updating flow scripts and tool configurations, and building and running regression test cases that prove each Back-End step runs successfully.
We are in the middle of a genuine modernization: consolidating Back-End construction, verification, and analysis into a new unified flow environment with managed workspaces and released collateral, replacing inherited infrastructure with solutions we own end to end. A senior engineer joining now will have the opportunity to shape how the next several process nodes are enabled.
You will work with other Design Automation teams and engineering experts across the globe to enable new process nodes for new projects.
We are actively applying AI and ML inside our design automation flows, including runtime and resource prediction, automated failure summarization and categorization in regressions, and knowledge capture from debug. AI-assisted development tools are also in everyday use across the Design Automation teams. If you want to bring these techniques into Back-End flow development and process node bring-up, you will find an organization already leaning in.
Responsibilities
Own the end-to-end bring-up, qualification, and production deployment of Back-End design automation flows for new process nodes and technology releases.
Partner directly with design leads, domain representatives, and technology enablement teams to understand new-node requirements and translate them into scalable Back-End methodologies and flows.
Integrate and qualify new PDKs, standard-cell libraries, Foundation IP, and other technology collateral, updating EDA tool configurations, flow scripts, and supporting infrastructure as required.
Develop, maintain, and execute comprehensive regression test cases to validate Back-End flow functionality, identify failures, and drive issues through resolution prior to production release.
Support Back-End design teams through production use and tape-out, including flow deployment, debug, user support, training, documentation, and methodology improvements.
Contribute to the modernization and consolidation of Back-End construction, verification, and analysis flows within a unified design automation environment with managed workspaces and released collateral.
Collaborate with globally distributed Design Automation teams and engineering experts to drive technical alignment, resolve cross-functional issues, and enable new process nodes across multiple projects.
Evaluate and apply AI/ML techniques and AI-assisted development tools to improve flow development, regression analysis, debug, runtime/resource optimization, and knowledge capture.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149,100 - $215,925 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Minimum Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related technical field, with 8+ years of professional experience in Back-End IC design or design automation.
8+ years of professional experience owning, developing, or supporting production Back-End design flows, including areas such as PDK installation and setup, custom design construction, circuit simulation, cell characterization, physical verification (DRC/LVS), RC extraction, static timing analysis, IR/EM, or power analysis.
8+ years of professional experience working with semiconductor process technologies, including direct experience bringing up or migrating design environments to new process nodes or technology releases, including PDK, standard-cell library, and technology collateral integration and qualification.
8+ years of professional experience using industry-standard Back-End EDA tools, including tools from Synopsys, Cadence, and/or Siemens.
8+ years of professional experience developing and maintaining software and automation for semiconductor design flows, including Python, Tcl, shell scripting, or similar languages, with a strong understanding of algorithms and data structures and experience releasing production flows through a formal process.
8+ years of professional experience working in Linux/UNIX environments with distributed compute infrastructure and job schedulers, including efficiently executing and managing large-scale design and regression workloads.
8+ years of professional experience partnering directly with IC design teams as internal customers, including gathering methodology requirements, deploying production flows, supporting users through tape-out, and developing technical training and documentation.
8+ years of professional experience driving technical alignment across geographically distributed engineering teams, including coordinating technical decisions and execution across multiple sites and time zones.
8+ years of professional experience communicating complex technical concepts to engineering audiences, including presenting Design Automation methodology proposals, technical recommendations, and project status to design leads and senior engineering management.