Senior ASIC RTL design engineer at Cerebras who drives wafer-scale AI chip design from functional spec and microarchitecture through RTL development and synthesis, then debugs silicon during bring-up. Day-to-day involves high-performance RTL, front-end and third-party IP integration, and collaboration across physical design, verification, DFT, and software teams.
You will design and develop next-generation wafer-scale-engine RTL and integration solutions. You will drive chip design from functional specification and microarchitecture through RTL development and synthesis, work with physical design, verification, DFT, software, and system partners, and debug silicon functional, timing, and power issues during bring-up.
Responsibilities
Drive chip design from functional specification and microarchitecture through RTL development and synthesis
Collaborate with physical design teams to achieve PPA goals
Collaborate with design verification and DFT teams to improve functional and test coverage
Partner with software and system teams to optimize product performance and features
Debug silicon-level functional, timing, and power issues during bring-up
Requirements
Master’s degree in Computer Science, Electrical Engineering, or equivalent
Ability to work in a hybrid work environment
8+ years of experience delivering complex, high-performance RTL designs
Experience with front-end chip integration and third-party IP integration
Experience in high-performance computing, GPU or CPU designs, machine learning, or related fields
Track record of multiple successful silicon deliveries
Experience collaborating with external vendors
Networking stack experience including TCP/IP, RDMA, and Ethernet
Knowledge of PCIe, CPU interfaces, and Serdes technology
Working knowledge of Python and TCL scripting tools