Senior Architect (GPU/NPU Frontier Technology & System Innovation)

About the Role

We are developing next-generation NPUs and computing systems with large-model inference as a primary application, and are looking for a senior architect with technical depth and a systems perspective to drive hardware architecture innovation, frontier technology exploration, and validation of key technical solutions.

This role is centered on hardware architecture and requires combined hardware/software knowledge and analytical capability — understanding the execution characteristics of large models, compilers, and runtimes, and translating them into design and optimization decisions across chips, memory, interconnect, and complete systems. Strong emphasis is also placed on performance, energy efficiency, cost efficiency, and engineering feasibility under domestic process and supply-chain conditions.

We welcome technical experts with deep expertise in at least one of the following areas — NPU chips, high-speed interconnect, or complete systems — and with a cross-domain perspective.

Key Responsibilities

1. Hardware architecture exploration for large-model inference. Research NPU compute architecture, memory hierarchy, data movement, and interconnect mechanisms around the requirements of large-model inference, and propose innovative ideas, architecture improvements, and alternative solutions with product value.
2. Workload analysis and hardware-software co-design. Analyze the compute, memory-access, and communication characteristics of representative models in stages such as Prefill and Decode; combined with operator mapping, compiler scheduling, runtime, and communication libraries, identify hardware bottlenecks and optimize resource allocation and hardware-software interfaces.
3. Focused research on key hardware technologies. Based on individual expertise, lead research and solution design in one or more of the following directions:

• NPU and SoC architecture: compute units, memory hierarchy, NoC, memory controllers, host interfaces, and related IP.
• Advanced packaging and memory: chiplet, 2.5D/3D packaging, stacked memory, and die-to-die interconnect.
• Boards and multi-card interconnect: PCIe accelerator cards, OAM modules, inter-card interconnect, system topology, and communication mechanisms.
• Systems and supernodes: multi-accelerator servers, rack-scale systems, and supernodes, balancing compute, interconnect, power, cooling, and mechanical constraints.

1. Domestic process adaptation and engineering feasibility. Evaluate constraints such as die area, frequency, power, yield, and interface capabilities against the maturity of domestic wafer fabrication, memory, packaging, substrate, and IP capabilities, and explore architecture implementation paths suited to the domestic supply chain.
2. Performance and cost-efficiency optimization. Under target model, precision, and service-latency requirements, evaluate effective throughput, energy efficiency, and multi-card scaling efficiency; factoring in manufacturing, packaging, testing, memory, board, and system costs, optimize inference capability per unit cost and total cost of ownership (TCO).
3. Modeling, validation, and results delivery.

   Quantitatively compare the benefits and risks of candidate solutions through performance modeling, simulation, prototype verification, and sample testing; collaborate with chip, packaging, hardware, and software teams to move research outcomes into product design. Qualifications · Bachelor's degree or above in Microelectronics, Computer Science, Electronic Engineering, Communications, or a related field, with extensive hardware R&D experience and experience in architecture design, technology research, or complex system development.

   ·

   Chip direction:

   NPU or high-performance computing chips, with solid knowledge of compute units, memory hierarchy, on-chip interconnect, SoC integration, and related IP.

   • Hardware-software co-design knowledge that underpins hardware architecture design — understanding how models and operators are mapped to hardware through compilers and runtimes, and the ability to work with software teams to analyze performance issues and translate them into hardware requirements and design trade-offs.
   • A cross-layer systems perspective, able to understand the dependencies among chips, packaging, boards, interconnect, and complete systems.

   Expert-level depth in every direction is not required.

   • Understanding of domestic semiconductor process and supply-chain conditions, able to incorporate manufacturing, IP, packaging, and production constraints into solution evaluation.

   Preferred Qualifications

   • Architecture design experience with NPU chips or computing systems for large-model inference.
   • A proven track record of improving hardware utilization, inference performance, or deployment cost through hardware-software co-design.
   • Experience developing PCIe/OAM boards, multi-GPU servers, liquid-cooled racks, or supernodes.
   • Experience in joint development with foundries, packaging houses, IP vendors, or system manufacturers.

   The OpportunityThis role explores hardware innovation for next-generation NPU and computing systems grounded in the real-world needs of large-model inference, combining frontier technology with domestic engineering conditions to deliver product solutions with performance advantages, cost competitiveness, and mass-production viability. Specific research directions can be tailored to the candidate’s expertise.

4. · Experience in hardware performance modeling, system simulation, FPGA prototyping, or cost modeling.
5. · Project experience with chiplet, advanced packaging, stacked memory, UCIe, or multi-card high-speed interconnect.
6. · Experience in chip design, tape-out, mass production, or system productization based on domestic processes.
7. · Ability to conduct independent research on focused topics, track frontier technologies, propose new ideas, and validate technical judgments through modeling, data, and experiments.
8. · Strong cost awareness and engineering judgment, able to make sound trade-offs among performance, power, cost, development cycle, and supply-chain availability.
9. · Familiarity with the key characteristics of large-model inference, including Attention, MoE, low-precision computation, KV cache, Prefill/Decode, and model parallelism, and the ability to analyze their demands on compute, memory, and communication resources.
10. · Interconnect direction: high-speed SerDes, die-to-die, PCIe, dedicated inter-card interconnect, or RDMA networks, with an in-depth understanding of how topology, bandwidth, latency, and communication efficiency impact system performance.
11. · In-depth architecture design capability and hands-on project experience in at least one of the following areas: