Principal Design Automation Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Staff/Principal Design Engineer in the NVE Design Engineering organization at Micron Technology, Inc., you will drive the transformation of NAND circuit development through design automation, agentic circuit-design enablement, and environment transition!

• Implementing core Xpath, Ypath and Array design during project execution and work with project teams integrating the Core schematics into the full chip schematics, validating design performance and functionalities by running block and chip level simulations using standard industry simulators!
• Implementing analog and mixed signal circuit design (charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, LDO, thermometers, page buffers, PDNs, level shifters, IO buffers, RTL, Verilog) to meet specifications, validating design performance and functionalities by running block and chip level simulations using standard industry simulators
• Serve as a technical authority across analog/core teams, solving sophisticated technical problems at the intersection of circuit behavior, modeling, simulation methodology, and automation reliability
• Develop and productize agentic enablement for circuit design, including AI/LLM-assisted flows that support:
  • environment setup and self-healing configuration,
  • guided simulation and debug,
  • intelligent corner planning and coverage closure,
  • automated schematic/layout checks and review assistance,
  • documentation synthesis and knowledge retrieval from internal sources,
  • block/subsystem/full-chip verification (analog/mixed-signal), including reproducible run recipes, golden reference management, and regression gating criteria

• Integrate automation with project execution, partnering with circuit designers, firmware, validation, and architecture teams to align tooling with breakthrough needs and deliver measurable cycle-time reduction.
• Collaborate with multi-functional team members** (Product Engineering, Test, Probe, Process Integration, Assembly, Marketing) to ensure automation and environment choices support manufacturability, testability, reliability, time-to-market, and customer happiness.

Minimum Qualifications:

• MS (PhD preferred) in electrical engineering required. 8+ years of NAND design relevant proven experience required with proficient knowledge of Nand Flash memory read, program and erase algorithms
• Proficiency in analog/mixed signal circuit design (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL, Verilog)
• Proficiency in analog/mixed signal circuit layout (page buffers, block selectors, Xdecoder, Ydecoder, bias table and waveforms, PDNs, level shifters, charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, bandgap, IO buffers, RTL, Verilog)
• Proficient fundamentals in semiconductor and device physics and analog/mixed-signal circuit design. An understanding of semiconductor reliability issues including CHC, NBTI, stress, and snapback, as well as Electromigration (EM) and IR analysis.
• Proficiency in circuit verification and optimization, layout planning, parasitic extractions of the circuits, experience guiding layout. Strong understanding of circuit design verification flows, including block‑level, subsystem‑level, and full‑chip simulations, corner management, PVT/mismatch analysis, and results qualification. analog and digital simulators such as HSPICE, Fast SPICE, and Verilog
• Proven proficiency in Python for engineering automation, including development of maintainable scripts, libraries, or frameworks that collaborate with EDA tools for simulation control, data extraction, regression management, or reporting. Proficient with Cadence design, LVS/DRC tools and UNIX

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$176,000.00 - $298,000.00 a year

Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on .

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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