Physical Design Power Optimization and Modeling Engineer
NVIDIA · Israel, Yokneam ·
- Category
- Design
- Experience
- 1+ years
- Company size
- 1000+
Optimize power across physical design flows (RTL2GDS) for NVIDIA's networking silicon chips—synthesis, place-and-route, timing closure, and power estimation/modeling—using EDA tools from Synopsys and Cadence.
NVIDIA is looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
Power estimation and power modeling.
What we need to see:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
1+ years of experience in physical design and/or BE power optimization aspects.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Native ability to leverage modern AI tools to accelerate engineering workflows, productivity, and problem-solving.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
FE design experience is an advantage.
Excellent problem-solving, partnership, and interpersonal skills.
NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!