Physical Design Lead, Google Cloud

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you’ll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.

You’ll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Lead physical design of complex SoC to tape-out while working with multiple team members.
• Evaluate and develop physical design methodologies and decide on the SoC flow.
• Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
• Participate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
• Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• Experience in silicon implementation and chip integration.
• Experience in ASIC development teams.
• Experience in managing physical design teams working on digital designs that produce and deliver silicon.

Preferred qualifications:

• Experience in extraction of design parameters and analyzing data trends.
• Experience and breadth in engineering across physical design, top-level implementation, GDS tape-out.
• Experience in top-level floor planning, block integration, static timing analysis, and sign-off.
• Understanding of circuit design, device physics, and deep sub-micron technology.
• Knowledge of delivery of high complexity silicon in technology process nodes.
• Ability to lead cross-functional teams.